Abstract: In a method of generating compensation data for a display device, first color, second color, and third color compensation value sets may be obtained by capturing first color, second color, and third color images displayed by the display device, respectively, white, first color, second color, and third color loading luminances may be obtained by capturing white, first color, second color, and third color loading patterns displayed by the display device, respectively, first color, second color, and third color scale factors may be calculated by dividing a luminance decrease ratio of the white loading luminance by luminance decrease ratios of the first color, second color, and third color loading luminances, respectively, and the first color, second color, and third color compensation value sets and the first color, second color, and third color scale factors may be stored in the display device.

Abstract: A display device may include a backlight unit, a display panel, and a backlight driver, and a panel driver. The backlight unit may include light source blocks including a first light source block. The display panel may include dimming regions including a first dimming region and respectively overlapping the light source blocks. The first dimming region may overlap the first light source block. The backlight driver may control a turn-on period and a turn-off period of each of the light source blocks. The panel driver may sequentially provide scan signals to the dimming regions for controlling light transmission of the dimming regions. A turn-off period of the first light source block may start before a scan period of the first dimming region and may end after the scan period of the first dimming region. The first dimming region may receive corresponding scan signals in the scan period.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

Abstract: The present invention relates to a vinyl glove with a cosmetic pack function having a shape of a finger glove having finger portions and a body, the vinyl glove including: cutting lines formed along the finger portions to separate given portions of the finger portions from the body; finger bonding portions formed toward the body by given distances with respect to the cutting lines in such a manner as to thermally bond tops and undersides of the finger portions to prevent the cosmetic liquid from leaking to the outside; and a wrist bonding portion formed inward toward the body by a given distance with respect to an insertion portion formed on a wrist portion of the body in such a manner as to thermally bond top and underside of the body to prevent a cosmetic liquid from leaking to the outside.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: A display device includes a display panel including gate lines, data lines, and pixels individually connected to a corresponding gate line and data line, a gate driver driving the gate lines, a data driver driving the data lines, and a driving controller. The driving controller receives, from an external source, first image signals and a variable frequency signal indicating an operation frequency (frame rate) for the display device. The driving controller converts the first image signals to second image signals by adding a compensation value corresponding to the operation frequency to the first image signals, and outputs the second image signals to the data driver. Embodiments may compensate for luminance reduction/variation and reduce image artifacts that otherwise occur due to variable frequency operation. An alternative embodiment dynamically controls an amount of light output from a backlight according to the variable frequency signal.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A tube-pin assembly for a heat exchanger of a vehicle includes a housing having an inlet into which exhaust gas flows; a plurality of tubes arranged inside the housing to provide a passage through which the exhaust gas flows; and cooling pins provided between the tubes to provide a coolant passage through which coolant flows, where a foamed metal made of a porous material is provided inside at least one of the tubes.

Abstract: A core manufacturing apparatus using an inorganic binder includes a mulling sand feeder that supplies mulling sand comprising sand and the inorganic binder, a mold that receives the mulling sand from the mulling sand feeder and molds the mulling sand into a core, and a mold heating device that heats the mold. The mold includes an upper mold and a lower mold and has a plurality of cavities formed therein in which the mulling sand is deposited. The mold further includes an inner fluid channel through which fluid flows.

Abstract: A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

Abstract: A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

Abstract: A stage of a gate driving circuit includes: a first control transistor diode-connected between a first input end of the stage and a first node, biased by a first input signal, and back-biased by a second input signal; a second control transistor including a control end which receives a third input signal, a first end connected to the first node, and a second end connected to a first voltage, and back-biased by a fourth input signal; a first output transistor including a control end connected to the first node, a first end connected to a clock input end of the stage, and a second end connected to a first output end of the stage; and a capacitor connected between the control and second ends of the first output transistor. The second input signal and the fourth input signal have enable levels during different periods.

Abstract: A display device may include display pixels configured to emit light at a luminance corresponding to a data signal, at least one auxiliary pixel configured to store an auxiliary voltage, a gate driver configured to supply a gate signal to the display pixels and the auxiliary pixel, a data driver configured to convert image data into the data signal, and supply an auxiliary voltage having a preset level to the auxiliary pixel. A sensing circuit is configured to sense a change in the auxiliary pixel for each frame, and generate compensation voltage information. A timing controller is configured to convert an image signal into the image data, and generate a driving voltage control signal. A voltage generation unit is configured to generate a driving voltage corresponding to the driving voltage control signal, and generate the reference gamma voltage based on the driving voltage.

Abstract: An nth (where n is a natural number) stage is included in a scan driver of a display. The nth stage includes: a first input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage; a second input circuit for controlling the voltage of the first node in response to a carry signal of a next stage; a first control circuit for controlling a voltage of an output terminal in response to the carry signal of the next stage; an output circuit for outputting an nth scan signal and an nth carry signal in response to the voltage of the first node and a voltage of a second node; and a leakage control circuit for supplying a control voltage to the first input circuit and the second input circuit in response to one of the nth scan signal and the nth carry signal.

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.