Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.

Abstract: An embodiment of a pseudo nonvolatile memory device incorporating a high capacity micro battery includes a DRAM chip having bonding pads. The DRAM chip may be attached to a frame. The frame may have external connecting terminals corresponding to the bonding pads. Wires are provided for electrically connecting the bonding pads to corresponding external connecting terminals. The bonding pads and the wires may be covered with an encapsulant. A micro battery is provided over the DRAM chip. The micro battery may supply power to the DRAM chip.

Abstract: A method of forming a carbon nanotube includes forming a cavity between a substrate and a first layer on the substrate. The cavity extends in a wiring pattern and includes a metal catalyst pattern in the cavity. The carbon nanotube is formed from the metal catalyst pattern and extends inside the cavity along the wiring pattern. Related methods and devices are also discussed.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

Abstract: The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a carbon nanotube memory, an atomic memory, a single electron memory, or a memory fabricated by a chemical bottom-up method, etc.

Abstract: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.

Abstract: Provided is a method of forming carbon nanotubes. The method includes modifying the surfaces of catalyst nano particles using a surface modifying agent containing silicon such as 3-aminopropyltriethoxysilane, and growing the carbon nanotubes on the modified surfaces of the catalyst nano particles so that the diameter of the carbon nanotubes is controlled by the surface modification. The diameter of the carbon nanotubes is controlled by surface steric stabilization resulting from a silicon oxide deposit deposited on the surfaces of the catalyst nano particles through the decomposition of the surface modifying agent.

Abstract: A non-volatile memory device includes a channel region defined between a source region and a drain region, a charge storage film disposed on the channel region to store a charge, and a tunnel insulating film interposed between the channel region and the charge storage film to tunnel the charge, the tunnel insulating film having a quantum confinement film.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: In a method of forming a thin layer having a desired composition, a source gas is provided onto a substrate loaded in a chamber for a first time, and the source gas is chemisorbed onto the substrate. While the source gas is provided, a plasma is generated in the chamber for a second time to change the chemisorbed source gas into the thin layer having the desired composition. The thin layer may have a stoichiometrical composition or a non-stoichiometrical composition.

Abstract: A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

Abstract: Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region. Methods of forming single transistor floating body dynamic random access memory (DRAM) cells are also provided.

Abstract: Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conductive catalyst material. This catalyst material may be selected from the group consisting of iron, nickel and cobalt and alloys thereof.

Abstract: The present invention provides methods of forming uniform nanoparticle based monolayer films with a high particle density on the surface of a substrate comprising (a) forming a surface modifying layer on a substrate using a material comprising a first functional group that chemically binds to the substrate and a second functional group comprising a group capable of forming van der Waals forces, (b) applying to the surface modifying layer a solution comprising nanoparticles, and (c) curing the resultant structure formed at step (b) for a predetermined time to form a nanoparticle based monolayer film. The present invention further provides substrates and devices comprising the nanoparticle based monolayer films.

Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.