Abstract: Provided is a memory device. The memory device includes a module board on which one or more semiconductor devices are disposed and a conductive plate mounted on a first side of the module board. The conductive plate includes a shielding region and a non-shielding region. A pad is disposed in the shielding region of the conductive plate.

Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.

Abstract: A wireless power transmitter for wirelessly transmitting power to a wireless power receiver is provided. A wireless power transmitter according to various embodiments may include: a driving unit that provides power; and a power transmission unit that wirelessly transmits power to the wireless power receiver based on the power received from the driving unit, wherein the power transmission unit may include at least one capacitor; a first coil connected to the at least one capacitor, and a second coil connected to the at least one capacitor and disposed parallel to the first coil.

Abstract: A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

Abstract: A semiconductor device includes a phase difference detection circuit and an internal circuit. The phase difference detection circuit generates first and second phase difference detection signals by comparing a phase of a phase detection clock signal, generated from a command/address signal in synchronization with a clock signal, with phases of a division clock signal and an internal division clock signal that are generated by dividing a frequency of a data clock signal according to an operation mode. The internal circuit recognizes the phases of the division clock signal and the internal division clock signal according to a logic level combination of the first and second phase difference detection signals.

Abstract: Provided is a virtual image display device including: an image generator outputting a virtual image; a filter transmitting light in a first polarization state in the output virtual image; a multipath optical element guiding the transmitted light in the first polarization state; a first optical element arranged on a first side of the multipath optical element and allowing the guided light in the first polarization state and real-world light to pass therethrough; a second optical element arranged on a second side opposite to the first side of the multipath optical element and allowing the real-world light to pass therethrough; and a processor controlling the image generator, the first optical element, and the second optical element.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A solid state drive apparatus includes a case including a base and side walls extending upward along a circumference of the base, an electrostatic prevention structure of a metal pillar spaced apart from the side walls and protruding from at least a partial surface of the base and an electrostatic absorbing member on at least a partial surface of the metal pillar, a package substrate module mounted on the electrostatic prevention structure in the case, and a cover covering the case and the package substrate module.

Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D

Abstract: An optical system is provided which includes a light source which outputs light; a first waveguide; a transmissive reflective layer provided on a top surface of the first waveguide and configured to reflect some light and transmit the remaining light incident thereon; a second waveguide provided on a top surface of the transmissive reflective layer; an in-coupler provided on the first waveguide and configured to allow the light output by the light source to enter the first waveguide; and an out-coupler provided on one of the first waveguide and the second waveguide and configured to emit light from the optical system.

Abstract: Apparatuses, systems, and methods of wireless power transmission/reception are described. In one wireless power transmission/reception device, a planar resonator capable of generating magnetic fields has one or more ferrite members mounted thereon such that the magnetic fields generated by the planar resonator have an overall direction substantially tilted or parallel to its opening/face, i.e., to the plane of the planar resonator. In a wireless power reception device, the planar resonator generates magnetic fields and an induced current when being resonated by external magnetic fields; in a wireless power transmission device, the planar resonator generates magnetic fields when being supplied with power.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data

Abstract: A wireless power transmitter and a method for detecting a change in load during wireless charging in the wireless power transmitter is provided. The wireless power transmitter includes a power transmission unit configured to transmit power to a wireless power receiver, a current detection unit configured to measure a voltage value corresponding to a current that is output to the power transmission unit while the power is transmitted from the power transmission unit, and a controller configured to adjust the power transmitted by the power transmission unit based on the measured voltage value.