Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.

Abstract: A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an nth memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.

Abstract: Auxiliary power management devices are disclosed. In some implementations, an auxiliary power management device may be coupled to an auxiliary power source that serves as a backup power supply for a primary power source to provide power to an electronic device and comprising a plurality of switches to control currents of a plurality of energy storage components, a plurality of channels coupled to the plurality of switches, respectively, a plurality of switch controllers to control the plurality of switches coupled to the plurality of channels and monitor a current or voltage of the plurality of channels, and a management logic to control the switches coupled to the plurality of channels upon detection, by the plurality of switch controllers, of a first current or voltage distribution across the channels that exceeds a predetermined threshold regarding the current or voltage distribution.

Abstract: A memory system includes a memory device and a memory controller for providing data to the memory device based on a clock signal. The memory device includes a first memory group; a second memory group; an internal clock generator for generating a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal; and a data distributor for providing the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.

Abstract: A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an nth memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.

Abstract: A power supply apparatus may include a charging circuit configured to receive an external voltage and to generate a charging voltage by charging and discharging energy by switching according to a level of the charging voltage; an auxiliary power circuit configured to store an electric charge using the charging voltage; and a health monitoring circuit configured to determine a charging health state of the auxiliary power circuit by counting a number of switchings of the charging circuit during an interval in which the charging voltage rises to a first level from a second level, the determined charging health state being based on the number of switchings.

Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the one memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.

Abstract: A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an nth memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.

Abstract: Auxiliary power management devices are disclosed. In some implementations, an auxiliary power management device may be coupled to an auxiliary power source that serves as a backup power supply for a primary power source to provide power to an electronic device and comprising a plurality of switches to control currents of a plurality of energy storage components, a plurality of channels coupled to the plurality of switches, respectively, a plurality of switch controllers to control the plurality of switches coupled to the plurality of channels and monitor a current or voltage of the plurality of channels, and a management logic to control the switches coupled to the plurality of channels upon detection, by the plurality of switch controllers, of a first current or voltage distribution across the channels that exceeds a predetermined threshold regarding the current or voltage distribution.

Abstract: Methods of programming firmware in a data storage device include pre-programming memory cells included in at least one nonvolatile memory of a plurality of nonvolatile memories using a first verification voltage higher than a first reference voltage before a surface mounting technology is applied to the nonvolatile memories.

Abstract: Methods of programming firmware in a data storage device include pre-programming memory cells included in at least one nonvolatile memory of a plurality of nonvolatile memories using a first verification voltage higher than a first reference voltage before a surface mounting technology is applied to the nonvolatile memories.

Abstract: A solid state drive in accordance with embodiments of the present inventive concepts may include a nonvolatile memory, a volatile memory, a memory controller controlling the nonvolatile memory and the volatile memory, and a power generator providing power to the nonvolatile memory, the volatile memory, and the memory controller. A method of operating the solid state drive may include designating a bank that will perform a self refresh among a plurality of banks included in the volatile memory in response to a power saving mode signal. Information of the designated bank may be stored in a register in response to a command and an address signal; and a self refresh of the designated bank may be performed on the basis of the information stored in the register.

Abstract: A memory system includes a package having a memory device, and a wiring board to which the package is attached. The wiring board includes a first region and a second region separable from the first region. The first region may conform in terms of its dimensions and other physical characteristics to a first form factor of the memory system, and the first and second regions collectively may conform in the same way to a second form factor of the memory system.

Abstract: An auxiliary power supply device can include a first power storage unit, a first charging circuit to receive input power and charge the first power storage unit, a second power storage unit having lower power supply speed than the first power storage unit and longer power supply time than the first power storage unit, a second charge circuit to receive input power and charge the second power storage unit, and a switching unit to supply the stored power of the first power storage unit to external devices for a predetermined time when a sudden power-off occurs and supply stored power of the second power storage unit to the external devices after the predetermined time elapses.

Abstract: A secondary memory device includes a substrate configured to receive power from an external power source, at least one of non-volatile memory devices mounted on the substrate, a control device mounted on the substrate to control the non-volatile memory devices, and a secondary battery electrically connected to the substrate and configured to supply second power to the substrate when a power supply from the external power source is abnormally stopped.

Abstract: A solid state drive in accordance with embodiments of the present inventive concepts may include a nonvolatile memory, a volatile memory, a memory controller controlling the nonvolatile memory and the volatile memory, and a power generator providing power to the nonvolatile memory, the volatile memory, and the memory controller. A method of operating the solid state drive may include designating a bank that will perform a self refresh among a plurality of banks included in the volatile memory in response to a power saving mode signal. Information of the designated bank may be stored in a register in response to a command and an address signal; and a self refresh of the designated bank may be performed on the basis of the information stored in the register.

Abstract: An auxiliary power supply device can include a first power storage unit, a first charging circuit to receive input power and charge the first power storage unit, a second power storage unit having lower power supply speed than the first power storage unit and longer power supply time than the first power storage unit, a second charge circuit to receive input power and charge the second power storage unit, and a switching unit to supply the stored power of the first power storage unit to external devices for a predetermined time when a sudden power-off occurs and supply stored power of the second power storage unit to the external devices after the predetermined time elapses.

Abstract: A data storage device includes a voltage supply control circuit configured to receive an external voltage, generate different voltages from the external voltage, and supply the different voltages to loads, respectively, through voltage supply lines, respectively and a discharge control circuit configured to discharge residual voltages from the voltage supply lines in response to a control signal and the external voltage, the discharge control circuit configured to discharge the residual voltages in an order of a highest residual voltage to a lowest residual voltage.

Abstract: A charging device of a robot cleaner is provided. The charging device of a robot cleaner according to the embodiment includes at least one cover forming an appearance of the charging device, a base which is coupled with the cover and includes a terminal unit for charging the robot cleaner, an induction signal generating unit disposed at a side of the cover or the base to transmit a return induction signal to the robot cleaner, and an induction signal guide member disposed at a side of the induction signal generating unit to enhance a docking performance of the robot cleaner by improving linearity of the induction signal. The charging device according to the embodiment can guide the path for the return of the robot cleaner and recharge the robot cleaner stably.

Abstract: A charging device of a robot cleaner is provided. The charging device of a robot cleaner according to the embodiment includes at least one cover forming an appearance of the charging device, a base which is coupled with the cover and includes a terminal unit for charging the robot cleaner, an induction signal generating unit disposed at a side of the cover or the base to transmit a return induction signal to the robot cleaner, and an induction signal guide member disposed at a side of the induction signal generating unit to enhance a docking performance of the robot cleaner by improving linearity of the induction signal. The charging device according to the embodiment can guide the path for the return of the robot cleaner and recharge the robot cleaner stably.