Abstract: A method, a computer readable medium and an apparatus to adaptively control a data transmission rate of a wireless display device. The method includes determining a current data transmission rate capacity of a wireless channel; and controlling a data transmission rate of a wireless transmission device based on the current data transmission rate capacity.

Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: An apparatus and a system, as well as a method and article, may operate to include repeating first data to provide first repeated data and deleting second repeated data to provide second data according to a programmed standard included in a first apparatus and selected from a plurality of reprogrammable standards.

Abstract: A reconfigurable decoder is capable of performing both Viterbi decoding and turbo decoding. The reconfigurable decoder may be repeatedly reconfigured to work with any of a number of different convolutional or turbo coding schemes. In at least one embodiment, the reconfigurable decoder is capable of automatically reconfiguring itself based on a present signal environment about a communication device carrying the decoder.

Abstract: In one embodiment of the invention, a memory receives unsynchronized data and a processor performs symbol interleaving at a synchronization point located after a beginning of a superframe.

Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption. The status indicators may indicate the status of routers coupled to the processors. Additional apparatus, systems, and methods are disclosed.

Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: An apparatus includes a primary information storage unit, a secondary information storage unit, and an information processing unit. The primary information storage unit has a primary storage capacity. The secondary information storage unit has a secondary storage capacity. The secondary storage capacity is less than the primary storage capacity. The secondary information storage unit receives information from the primary information storage unit and the information processing unit processes the information to form a transform.

Abstract: In various embodiments, a processing element (PE) includes a data router adaptor (DRA) and one or more elements that produce function packets. When the DRA receives a function packet, it generates a set of associated router packets. Each of the associated router packets includes a segment of the function packet, and has a router packet data length that is less than or equal to the function packet length. In one embodiment, the router packet data lengths are included in a table, and can be re-configured to alter system performance parameters (e.g., bandwidth usage and/or latency). The DRA sends the set of associated router packets to a router for delivery through a packet-based network. A destination DRA receives the set of associated router packets, and generates a re-assembled function packet from the set of associated router packets. The destination DRA sends the re-assembled function packet to a destination element.

Abstract: Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.

Abstract: Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.

Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: An apparatus and a system, as well as a method and article, may operate to include repeating first data to provide first repeated data and deleting second repeated data to provide second data according to a programmed standard included in a first apparatus and selected from a plurality of reprogrammable standards.

Abstract: An apparatus and a system, as well as a method and article, may operate to include repeating first data to provide first repeated data and deleting second repeated data to provide second data according to a programmed standard included in a first apparatus and selected from a plurality of reprogrammable standards.

Abstract: Interleaving/de-interleaving may be performed by transferring multi-byte data blocks to be interleaved or de-interleaved into a set of memory banks on a column-by-column basis, transferring the data blocks to a data memory on a row-by-row basis, transferring the data blocks back to the memory banks on a row-by-row basis, using a set of shifted addresses that may cause cyclic shifting of the row orders, and transferring the interleaved or de-interleaved data blocks out of the memory banks on a column-by-column basis. The roles of rows and columns may, equivalently, be reversed.

Abstract: An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.

Abstract: A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the special function units, and a global memory to facilitate processing by these units. Each control unit may have an array of programmable logic arrays (ARPLAs), each of which may be configured in various ways, a local memory, and a switch circuit to enable the components of the control unit to perform various operations. By configuring the ARPLAs, the control units' internal switch circuitry, and the cross-bar switch, the micro-coded accelerator may be dynamically reconfigured to perform multiple types of operations.

Abstract: A method and apparatus for communicating within a segmented network are generally disclosed.

Abstract: A multi-read buffer latches a start read address of a read pointer of multicast packet data in response to a multi-read mode signal. The read pointer is incremented during a read of the multicast packet data, and the latched start read address is reloaded to the read pointer after the multicast packet data is read for a subsequent reading of the multicast packet data for a next multicast packet. In some data-processing embodiments, the multi-read buffer may be provided between two or more processors of a multi-processor system. In these embodiments, portions of packet data may be validated and reread from buffer by one of the processors.

Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption.