Abstract: A method for detecting a leakage current path in a circuit is presented. The method may be used for identifying a leakage current path in an analog circuit and induced by the presence of a high voltage. The method includes several steps. A circuit design description of the circuit is received. The circuit design description is then interrogated to identify a set of candidate components having a first terminal coupled to a voltage source adapted to provide a voltage above a predefined value. Then for each electronic component in the set, a second terminal coupled to ground is searched. Upon identification of the second terminal coupled to ground a leakage path is reported. The method may be used for identifying a leakage current path induced by the presence of a high voltage in conjunction with the presence of parasitic devices.

Abstract: A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

Abstract: A method to provide an automated circuit design tool that mitigates or overcomes the inefficiencies present in the prior art tools ensuring a more efficient use of computer resources and a reduction in the time taken to design a suitable circuit that meets the design specification is presented. The computer-implemented method of designing a circuit configuration of a circuit, has the following steps 1) providing a first set of circuit configurations comprising one or more circuit configurations, 2) simulating each, circuit configuration of the first set of circuit configurations. In addition, the steps include: 3) scoring each, circuit configuration of the first set of circuit configurations based on a design specification and the simulation, or simulations, of step 2), and 4) providing a second set of circuit configurations comprising one or more circuit configurations that are dependent on the scores as determined in step 3).

Abstract: Technologies for monitoring a characteristic of a monitored system include determining a measured value of the primary characteristic of the monitored system sensed by a primary sensor and a measured value of the secondary characteristic of the monitored system sensed by a secondary sensor, and predicating a predicted value of the primary characteristic based on the measured value of the secondary characteristic. The measured and predicted values of the primary characteristic are used to determine whether the primary sensor is properly functioning.

Abstract: Technologies for monitoring a characteristic of a monitored system include determining a measured value of the primary characteristic of the monitored system sensed by a primary sensor and a measured value of the secondary characteristic of the monitored system sensed by a secondary sensor, and predicating a predicted value of the primary characteristic based on the measured value of the secondary characteristic. The measured and predicted values of the primary characteristic are used to determine whether the primary sensor is properly functioning.

Abstract: A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column. The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.

Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.

Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.