Patents by Inventor Indrajit Manna

Indrajit Manna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050056896
    Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 17, 2005
    Inventors: Indrajit Manna, Keng Lo, Pee Tan, Michael Cheng
  • Patent number: 6842078
    Abstract: A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: January 11, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Indrajit Manna, Lo Keng Foo
  • Publication number: 20040189407
    Abstract: A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Indrajit Manna, Lo Keng Foo
  • Patent number: 6724214
    Abstract: A first on-chip test structure monitors hot carrier degradation. A degrading ring oscillator is subjected to hot carrier effects while a non-degrading ring oscillator is not. As the device ages, hot carrier effects degrade the degrading ring counter. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same that experienced by percentage of gates under normal usage. A drop in the resistance indicates breakdown of a capacitor. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied such that the time to failure of all metal lines is the same as that experienced by a percentage of minimum width metal lines under normal usage. An increase in resistance indicates breakdown of a metal line.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: April 20, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Indrajit Manna, Lo Keng Foo, Guo Qiang, Zeng Xu
  • Publication number: 20040051553
    Abstract: Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation.
    Type: Application
    Filed: September 13, 2002
    Publication date: March 18, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Indrajit Manna, Lo Keng Foo, Guo Qiang, Zeng Xu