Abstract: The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store multiple bits feasible. An N-type or a P-type MOS device of the standard CMOS process or a flat-cell mask ROM process are operable devices and processes in the design of this multi layer cell ROM. The ROM cell with smaller size is implemented to represent the LSB bits, while the larger size ROM cell is to represent the MSB bits.

Abstract: A non-volatile memory and method of fabricating the same are provided. The method of fabricating a non-volatile memory comprises forming a tunnel insulating layer, a first conductive layer and a first patterned hard mask layer on a semiconductor substrate sequentially. A first conductive pattern is formed by etching the first conductive layer using the first patterned hard mask layer as a mask. The first patterned hard mask layer is removed. A second patterned hard mask layer is formed on an edge of the first conductive pattern. A pair of opposing spacers is formed on sidewalls of the second patterned hard mask layer. The first conductive pattern is etched using the second patterned hard mask layer and the spacers as masks to form a pair of stacked structures comprising the spacers, the second patterned hard mask layer and the remaining first conductive pattern. A pair of inter gate insulating layers are formed on sidewalls of the first conductive pattern.

Abstract: A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation layer is formed on the first opening sidewall to form a second opening. The first conductive layer and the first insulation layer beneath the second opening are etched to expose the substrate surface, and a spacer is formed on the second opening sidewall. A source region is formed in the exposed substrate and a source line with a concave surface is formed in the second opening. A mask layer is formed on the source line concave surface.

Abstract: The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store multiple bits feasible. An N-type or a P-type MOS device of the standard CMOS process or a flat-cell mask ROM process are operable devices and processes in the design of this multi layer cell ROM. The ROM cell with smaller size is implemented to represent the LSB bits, while the larger size ROM cell is to represent the MSB bits.

Abstract: A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation layer is formed on the first opening sidewall to form a second opening. The first conductive layer and the first insulation layer beneath the second opening are etched to expose the substrate surface, and a spacer is formed on the second opening sidewall. A source region is formed in the exposed substrate and a source line with a concave surface is formed in the second opening. A mask layer is formed on the source line concave surface.

Abstract: A method of forming a polysilicon spacer with a vertical profile. A dielectric layer and a sacrificial layer are successively deposited to cover the entire surface of a polysilicon layer that covers an insulating structure. Then, CMP is used to remove parts of the sacrificial layer, the dielectric layer and the polysilicon layer to reach a planarized surface. Then, a part of the polysilicon layer outside the insulating structure is removed to make the insulating structures protrude from the top of the polysilicon layer. After removing the sacrificial layer, forming a second oxide layer on the exposed surface of the polysilicon layer and removing the dielectric layer, dry etching is used to remove the polysilicon layer that is not covered by the second oxide layer. The polysilicon layer left under the second oxide layer serves as a polysilicon spacer with a vertical profile.

Abstract: In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Then form a mask over the stack and etch through the mask to pattern the oxide layers to form cavities in the stack of oxide layers reaching down through the stack to the sublayer. Then perform differential etching of the oxide layers in the cavities. Form undercut edges in the doped oxide layers with the undoped oxide layers having cantilevered ribs projecting from the stacks into the cavities to complete the cavities. Deposit a bulk/thick film monolithic conductive layer into the cavities to form a monolithic capacitor core with counterpart cantilevered ribs.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A gate structure is patterned on a substrate. An ion implantation is performed to form the LDD. Then, a thin liner layer is deposited on the feature of the substrate. A disposable spacer is successively formed attached on the side of the linear layer. The source and drain is next created in the substrate by ion implantation. The disposable spacer is then stripped by wet dip technique. A borderless layer is formed on the surface of the linear layer. A dielectric layer is formed on the gate structure and the dielectric layer can be composed of silicon dioxide, BPSG, SOG. Then, a photoresist is patterned on the dielectric layer to define the contact hole.

Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer.

Abstract: A method for fabricating a conducting structure for a semiconductor device is described. A first dielectric layer is formed on a substrate. The first dielectric layer is etched by using a first photoresist layer, to form original contact holes for exposing surface of the substrate. The first dielectric layer is etched by using a second photoresist layer which is aligned with desired contact holes selected from the original contact holes, to broaden top region of part of the desired contact holes as offset landing regions. A conductive layer is deposited in the desired contact holes, which includes the offset landing region, original contact holes, and on the first dielectric layer. Surface of the conductive layer is planarized to expose the first dielectric layer. In this planarization, original contact structures and desired contact structures having landing plugs are formed, which landing plugs are defined by the first and second photoresist layer.

Abstract: A conducting structure of a COB cell of DRAM includes an piecewise straight active area and substantially straight bitline formed over a semiconductor substrate upon which a first dielectric layer existed. Contact holes are formed over the piecewise straight active area for electrically exposing both nodes (source and drain), of the active area of the access device. An offset landing plug pattern is defined by a photoresist-clear pattern beside, say, the source node of the primary contact pattern and recess-etched into the first dielectric layer and electrically connected to the source node of the primary contact structure finally. The contact structure is then formed by a deposition-etched process, which performs as a landing plug for contact of the upper contact structures. The top area of the landing plug is defined through the additive pattern of the primary contact as well as the offset landing plug pattern.

Abstract: A process of fabricating a tungsten bit line structure, capped with a composite insulator shape, has been developed. The process features the use of a silicon oxide component, used as part of the capping, composite shape, employed to reduce the coupling capacitance generated by the proximity of the tungsten bit line structure, to adjacent conductive structures. The silicon oxide component is formed on an underlying, thin silicon nitride shape, which in turn overlays the tungsten bit line structure, preventing oxidation of the tungsten surface during the silicon oxide deposition. A capping, silicon nitride shape is placed on the underlying silicon oxide component. The use of this sandwich, or composite insulator shape, allows a tungsten bit line structure, with a sheet resistance between about 1 to 3 ohms/square, to be realized, with a reduction in coupling capacitance, in turn realized via the use of the silicon oxide component.

Abstract: A method for implementing shallow trench isolation by using a non-critical chemical mechanical polishing method in an integrated circuit. After STI regions are etched and insulator oxide layer is deposited and etched back, a planarized insulator oxide layer is formed. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Thereafter, a non-critical CMP process is used to polish the cap layer on the smaller active regions, then the insulator oxide layer under cap layer is removed by wet etch. Subsequently, a wet etch is used to remove the cap layer and silicon nitride layer. Finally, the shallow trench isolation process is completed after the pad oxide is removed.

Abstract: The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate (i.e, n-type) to form drain and source regions. A gate is formed between the drain and source regions having a gate oxide adjacent the substrate, a first polysilicon region (Poly-1), tungsten silicide layer, and an oxide layer and SiyNx, respectively, on the gate oxide. SiyNx spacers cover the sides of the gate regions. Above the oxide layer are tetetraethylorthosilicate (TEOS) and borophosphosilicate (BPSG) layers. A second polysilicon layer (Poly-2) is patterned to form a bitline which contacts the source region. A layer of tungsten silicide, oxide, and SiyNx are formed on top of the bitline. SiyNx spacers surround the bitline. A crown-shaped capacitor contacts the drain region.

Abstract: A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.