Patents by Inventor Inki Kim

Inki Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190064394
    Abstract: A photonic diode includes a first meta-material structure having a first bar and a second meta-material structure having a second bar arranged in a direction perpendicular to the first bar. The first bar and the second bar are separated from each other. Further, the first bar and the second bar are at least partially overlapped when viewed from a light propagation direction.
    Type: Application
    Filed: August 30, 2018
    Publication date: February 28, 2019
    Inventors: Junsuk Rho, Minkyung Kim, Gwanho Yoon, Inki Kim
  • Patent number: 10160825
    Abstract: A polyurethane elastomer including a polymerization product of an amide group-including compound, a polyol compound, a polybasic acid compound, and a diisocyanate compound, a thermoplastic resin composition including the polyurethane elastomer, a molded article made of the thermoplastic resin composition, and a method of preparing the polyurethane elastomer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inki Kim, Kyunghae Lee, Mooho Lee, Kwangmyung Cho
  • Publication number: 20160108167
    Abstract: A polyurethane elastomer including a polymerization product of an amide group-including compound, a polyol compound, a polybasic acid compound, and a diisocyanate compound, a thermoplastic resin composition including the polyurethane elastomer, a molded article made of the thermoplastic resin composition, and a method of preparing the polyurethane elastomer.
    Type: Application
    Filed: October 21, 2015
    Publication date: April 21, 2016
    Inventors: Inki Kim, Kyunghae Lee, Mooho Lee, Kwangmyung Cho
  • Patent number: 8637481
    Abstract: There is provided herein methods, compounds and methods for identifying compounds, for sensitizing a subject with cancer to a cancer therapy by inhibiting or down-regulating UROD.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: January 28, 2014
    Assignee: University Health Network
    Inventors: Fei-Fei Liu, Emma Ito, Inki Kim
  • Publication number: 20120094900
    Abstract: There is provided herein methods, compounds and methods for identifying compounds, for sensitizing a subject with cancer to a cancer therapy by inhibiting or down-regulating UROD.
    Type: Application
    Filed: April 12, 2010
    Publication date: April 19, 2012
    Applicant: University Health Network
    Inventors: Fei-Fei Liu, Emma Ito, Inki Kim
  • Patent number: 7259071
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: SilTerra Malaysia Sdn.Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7241665
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 10, 2007
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7208378
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: April 24, 2007
    Assignee: Silterra
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Publication number: 20060258116
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Application
    Filed: July 12, 2006
    Publication date: November 16, 2006
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Ping, Wan Lee, Choong Chien, Charlie Tay, Chang Lee, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7091104
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: August 15, 2006
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Gie Lee, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20050287745
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Application
    Filed: May 10, 2005
    Publication date: December 29, 2005
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Kim, Min Paek, Ong Teong, Oh Young, Ng Leng, Joung Ho
  • Patent number: 6890822
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: May 10, 2005
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Publication number: 20050059215
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Application
    Filed: October 25, 2004
    Publication date: March 17, 2005
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Kim, Min Paek, Chiew Ping, Wan Lee, Choong Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6818514
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 16, 2004
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20040166698
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 26, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20040161897
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 19, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Publication number: 20040147090
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Application
    Filed: January 23, 2003
    Publication date: July 29, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch?apos;ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Pin, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6290584
    Abstract: An improved workpiece carrier assembly includes a workpiece retaining assembly having a plurality of distinct retaining elements rather than a one-piece retaining ring. In accordance with one embodiment, a plurality of retaining segments reside within a like plurality of channels. The retaining segments may be individually or collectively controlled by a pressurized fluid system. In accordance with an alternate embodiment, a plurality of retaining pins reside within a like plurality of guide sleeves. The retaining pins may be individually or collectively controlled by a pressurized fluid system.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: September 18, 2001
    Assignee: SpeedFam-IPEC Corporation
    Inventors: Inki Kim, Mark Meloni, Mike Park
  • Patent number: 6113465
    Abstract: The present invention provides methods and apparatus for optimizing the removal of thin film layers during planarization of a semiconductor wafer to achieve global uniformity of the entire semiconductor surface while further achieving the planarity within an individual die structure. A wafer polishing system suitably comprises a wafer polishing apparatus, a controller and a wafer polishing recipe. The wafer polishing recipe may be comprised of various operational parameters utilized for controlling the operation of the polishing apparatus.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: September 5, 2000
    Assignees: SpeedFam-IPEC Corporation, Hewlett-Packard Company
    Inventors: Inki Kim, Jim Xu
  • Patent number: 6102779
    Abstract: In semiconductor wafer polishing, a backing pad is sized smaller than the wafer being polished so as to produce a desired backset, allowing the wafer to bend, thereby reducing over-polish at the wafer edge.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: August 15, 2000
    Assignee: Speedfam-IPEC, Inc.
    Inventors: Joseph V. Cesna, Inki Kim