Patents by Inventor Inkuk Kang

Inkuk Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190304990
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: March 4, 2019
    Publication date: October 3, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10242996
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20190027484
    Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 24, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20190027487
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 24, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Publication number: 20180166458
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel to the first surface, and top surfaces of the select gate and memory gate are approximately at or below an elevation of the planarized surface of the metal-gate. Generally, at least one of the top surfaces of the select gate or the memory gate includes a silicide formed thereon. Other embodiments are also disclosed.
    Type: Application
    Filed: October 12, 2017
    Publication date: June 14, 2018
    Applicant: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon KIM, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Patent number: 9853039
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: December 26, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Patent number: 9818755
    Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sung-Taeg Kang, James Pak, Unsoon Kim, Inkuk Kang, Chun Chen, Kuo-Tung Chang
  • Publication number: 20150255480
    Abstract: A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Application
    Filed: May 6, 2014
    Publication date: September 10, 2015
    Applicant: Spansion LLC
    Inventors: Tung-Sheng CHEN, Shenqing FANG, Inkuk KANG
  • Patent number: 8987092
    Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: March 24, 2015
    Assignee: Spansion LLC
    Inventors: Inkuk Kang, Gang Xue, Shenqing Fang, Rinji Sugino, Yi Ma
  • Patent number: 8742496
    Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 3, 2014
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Gang Xue, Wenmei Li, Inkuk Kang
  • Patent number: 8637918
    Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 28, 2014
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
  • Publication number: 20140001537
    Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Angela HUI, Shao-Yu TING, Inkuk KANG, Gang XUE
  • Publication number: 20130277732
    Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 24, 2013
    Inventors: Shenqing FANG, Gang XUE, Wenmei LI, Inkuk KANG
  • Patent number: 8551858
    Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 8, 2013
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Angela Hui, Shao-Yu Ting, Inkuk Kang, Gang Xue
  • Patent number: 8487373
    Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: July 16, 2013
    Assignee: Spanion LLC
    Inventors: Shenqing Fang, Gang Xue, Wenmei Li, Inkuk Kang
  • Publication number: 20120056260
    Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 8, 2012
    Applicant: Spansion LLC
    Inventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
  • Patent number: 8076199
    Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: December 13, 2011
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
  • Patent number: 8026169
    Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: September 27, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Alexander Nickel, Minh Q. Tran, Minh-Van Ngo, Hieu Pham, Erik Wilson, Hirokazu Tokuno, Amir Hossein Jafarpour, Inkuk Kang, Robert Huertas
  • Publication number: 20100276746
    Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Inventors: Shenqing FANG, Gang XUE, Wenmei LI, Inkuk KANG
  • Publication number: 20100207191
    Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong