EMBEDDED NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD OF THE SAME
Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
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This present application is a continuation of U.S. Non-Provisional application Ser. No. 15/848,439, filed on Dec. 20, 2017, which claims the priority and benefit of U.S. Provisional Application No. 62/534,512 filed on Jul. 19, 2017, the entire contents of which are hereby incorporated by reference.
BACKGROUNDNon-volatile memory (NVM) cells, such as flash memory cells, store data in computer memory systems. NVM cells may be formed on semiconductor substrates and include a number of transistors to provide memory functions and logic functions.
The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.
A split-gate non-volatile memory (NVM) cell can include a memory gate and a select gate formed on a semiconductor substrate. The split-gate configuration may provide improved size and efficiency characteristics compared to one transistor or two transistor NVM cell configurations. A split-gate memory cell may include a select gate to enable access to data stored in the memory cell and a memory gate that stores the data. In some implementations, the select gate and memory gate may be separated on a semiconductor substrate by one or more inter-gate dielectric layers.
While split-gate memory cells may provide some advantages in certain devices, integrating split-gate memory cells on a semiconductor substrate with certain logic devices may cause difficulties in fabrication. For example, certain advanced logic processes may use a high dielectric constant (high-k) gate dielectric with a metal gate (HKMG) to improve transistor performance and reduce leakage current. Some example high-k materials may include Hafnium Dioxide, Zirconium Dioxide, Titanium Dioxide, or the like. In some implementations, the high-K material may be characterized as having a dielectric constant greater than 2, 3, 3.5, or another value to provide proper functioning of the gate while reducing leakage currents. The HKMG may be fabricated using high-k dielectric material instead of a silicon based gate dielectric, such as silicon dioxide. In some implementations, however, fabrication of HKMG logic gates on the same substrate as a split-gate memory cell may cause shifts in the properties of the logic transistor. Additionally, differences in heights of a split-gate memory cell and a logic transistor may prevent proper fabrication of the memory cell or logic transistors during certain processing steps.
Disclosed herein are semiconductor devices and processes to integrate a split-gate NVM cell with a HKMG. The embedded devices may include a semiconductor substrate, such as Silicon, in a memory cell region of the substrate that is about the same height as the semiconductor substrate in a logic region of the device. For example, the substrate height in the different regions may be within approximately 200 angstroms of one another. The embedded device may also include upper surfaces of memory gates and select gates in the split-gate memory cell that are substantially co-planar. For example, the upper surface of the select gate and memory gate may be within approximately 300 angstroms of one another. Similarly, the upper surfaces of the select gate and memory gate may also be substantially co-planar with the upper surface of the HKMG logic transistor. This may reduce interference during logic gate replacement portions of a fabrication process. In some implementations, a silicide may also be formed on portions of the select gate or memory gate of a split-gate memory cell while silicide is not formed on a dielectric that separates the select gate and the memory gate.
Processes for fabricating a split-gate NVM cell embedded with an HKMG logic transistor may include fabricating the split-gate memory cell in a first region of a semiconductor substrate and a field-effect transistor (FET) with a high-k metal gate in a second region of the semiconductor substrate. Forming the split-gate memory cell may include forming a select gate (SG) and a memory gate (MG) adjacent to the select gate. In some implementations, the SG and MG may be separated by one or more layers of a dielectric. The logic FET may be formed on the same semiconductor substrate with a polysilicon gate, which may then be replaced with a metal gate. The high-k metal gate (HKMG) FET and the split-gate NVM memory cell may thus be formed on a semiconductor substrate having a substantially coplanar upper surface. Accordingly, in some embodiments, the semiconductor substrate may be substantially of similar thickness in both regions. For example, the SG, MG, and FET may be formed without creating a cavity or a recess in the substrate prior to deposition of elements of the gates. Furthermore, the heights of the SG, MG, and FET may be configured such that top surfaces of each of the SG, MG, and FET are substantially co-planar. Additional details of processing to fabricate the embedded split-gate memory device with a high-K metal gate FET are described in details with reference to the Figures below.
The split-gate memory cell 100 as described with reference to
When implemented in a semiconductor device, a number of split-gate devices 100 may be formed in a memory array. The memory array may be accessed with control circuitry to address particular memory cells. For example, row decoders and column decoders may be used to address memory cells based on a command received at control circuitry. Furthermore, sense amplifiers and word line or bit line drivers may be used to apply current to an addressed split-gate memory device and sense data stored in a memory gate 110 of the device.
The semiconductor substrate 220 may also include a logic FET region 227 that is separate from the memory region 225. In one embodiment, memory and logic FET regions 225 and 227 may be disposed adjacent to one another. In other embodiments, they may be disposed in different parts of the single semiconductor substrate 220. For example, the logic FET region 227 may be formed later in fabrication to include a high-k metal gate FET or other control circuitry for accessing memory cells in the memory region 225. In some implementations, the logic FET region 227 may also include other components or features in addition to a high-k metal gate FET. In one embodiment, semiconductor substrate 220 may have a relatively flat surface both in the memory region 225 and the logic FET region 227. The substrate 220 surfaces in the memory region and the logic FET region 227 are substantially co-planar, or are within 200 Angstrom of co-planar of one another.
In some implementations a memory gate polysilicon film 230 may be deposited on top of the oxide-nitride-oxide stack 210. As shown, the memory gate polysilicon film 230 may be deposited across the surface of the semiconductor substrate 220 including the logic FET region 227 and the memory region 225. A dielectric film 240 may be deposited on top of the memory gate polysilicon film 230 to act as a cap layer for the memory gate. In some implementations, the dielectric film may be about 20 Angstrom to about 500 Angstrom thick. In some implementations, a second polysilicon film 250 may also be deposited on top of the dielectric film 240 as an additional portion of the cap layer.
Beginning in block 410, a memory gate may be formed in a first region of a semiconductor substrate. For example, a memory gate may be formed as described with reference to
In block 420, a logic field-effect transistor is formed in a second (logic FET) region of the semiconductor substrates. The logic FET may have a high-K dielectric and is formed temporarily with a polysilicon gate. For example, the logic FET may be formed as described with reference to
In block 430, a select gate is formed adjacent to the memory gate in the first (memory) region of the semiconductor substrate. For example, the select gate may be formed by depositing a polysilicon film, etching back the polysilicon film such that the memory gate and select gate are substantially coplanar, and patterning the film to remove portions of the select gate. In some implementations, the select gate may be formed as describe above with respect to
In block 440 the polysilicon gate of the logic FET is replaced with a metal gate. After replacing the metal gate, devices formed in the memory region and in the logic FET region may be substantially co-planar. The height at which they are coplanar after a CMP process may expose either a hardmask on the sacrificial polysilicon gate or the sacrificial polysilicon gate itself. The sacrificial polysilicon gate may then be etched away with either a wet etching or dry etching process after patterning of a protective layer to protect the memory region. The metal gate may then be formed where the sacrificial polysilicon gate was removed. In some implementations, the metal may replace the polysilicon gate as described with reference to
In block 520 a select gate oxide may be formed underneath a polysilicon select gate layer. For example, the polysilicon select gate layer may be deposited as described above with reference to
In block 530, the polysilicon select gate layer may be leveled such that top surface of the polysilicon select gate layer is substantially coplanar with the top surface of the memory gate. For example, the polysilicon select gate layer may be leveled using a CMP process, or another process for developing a consistent plane on the surface of the device. In some implementations, the leveling or planarizing may be performed as described with reference to
In block 540, the planarized/leveled polysilicon select gate layer may be etched to remove portions of the polysilicon select gate layer disposed between two memory gates, for example on a source side of the split-gate memory cell. In some implementations, Tetramethylammonium hydroxide (TMAH) may be used as an exemplary wet etch chemical. For example, the wet etching or dry etching may be performed as discussed above with reference to
In block 550, additional portions of the polysilicon select gate layer may be removed to form the select gate. In one embodiment, the select gate may be formed adjacent to the memory gate on a drain side of the split-gate memory cell. For example, a polysilicon select gate layer may be removed with a lithography and etching process, such as dry etching or wet etching processes. In some implementations, the polysilicon select gate film may be removed as described with reference to
Additionally, some embodiments may be practiced in distributed computing environments where the machine-readable medium is stored on and or executed by more than one computer system. In addition, the information transferred between computer systems may either be pulled or pushed across the communication medium connecting the computer systems.
Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be in an intermittent and or alternating manner. The terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation. As used herein, the term “coupled” may mean connected directly or indirectly through one or more intervening components. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common on-die buses. Additionally, the interconnection and interfaces between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines and each of the single signal lines may alternatively be buses.
The above description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide an understanding of several embodiments of the present invention. It may be apparent to one skilled in the art, however, that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present invention.
Embodiments of the claimed subject matter include, but are not limited to, various operations described herein. These operations may be performed by hardware components, software, firmware, or a combination thereof.
The above description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide an understanding of several embodiments of the claimed subject matter. It may be apparent to one skilled in the art, however, that at least some embodiments of the may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the claimed subject matter.
Claims
1-20. (canceled)
21. A semiconductor device, comprising:
- a memory cell in a first region of a substrate, the memory cell including a polysilicon memory gate (MG) overlying a charge trapping layer; and
- a logic field-effect transistor (FET) including a metal gate disposed over a high-k dielectric in a second region of the substrate,
- wherein the MG of the memory cell and the metal gate of the logic FET have substantially a same height.
22. The semiconductor device of claim 21 wherein the memory cell is a split-gate memory cell further comprising a polysilicon select gate (SG) overlying a SG oxide layer, the SG formed adjacent to the MG and separated therefrom by an inter-gate dielectric.
23. The semiconductor device of claim 22 wherein top surfaces of the MG, the SG and the metal gate of the logic FET are substantially co-planar.
24. The semiconductor device of claim 23 wherein a first surface of the substrate in the first region and a second surface of the substrate in the second region of the substrate are substantially co-planar.
25. The semiconductor device of claim 23 wherein the inter-gate dielectric extends from the SG oxide layer to the top surfaces of the MG and the SG.
26. The semiconductor device of claim 23 wherein the top surface of at least one of the MG and the SG is silicided.
27. The semiconductor device of claim 23 wherein the top surfaces of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG.
28. The semiconductor device of claim 22 further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MG, the SG and the metal gate of the logic FET, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MG, the SG and the metal gate of the logic FET.
29. The semiconductor device of claim 22 wherein the charge trapping layer is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer.
30. A semiconductor device, comprising:
- a plurality of split-gate memory cells in a memory region of a substrate, each split gate memory cell including a polysilicon memory gate (MG) overlying a charge trapping layer, and a polysilicon select gate (SG) overlying a SG oxide layer formed adjacent to the MG and separated therefrom by an inter-gate dielectric; and
- a plurality of logic field-effect transistor (FET) in a logic region of the substrate, each logic FET including a metal gate disposed over a high-k dielectric,
- wherein top surfaces of each of the MGs, the SGs and the metal gate of the logic FETs are substantially co-planar.
31. The semiconductor device of claim 30 wherein the inter-gate dielectric in each split gate memory cell extends from the SG oxide layer to the top surfaces of the MG and the SG.
32. The semiconductor device of claim 30 wherein the top surfaces of each of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG in at least one of the split-gate memory cell.
33. The semiconductor device of claim 30 further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MGs, the SGs and the metal gate of the logic FETs, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MGs, the SGs and the metal gate of the logic FETs.
34. The semiconductor device of claim 30 wherein the charge trapping layer in each split gate memory cell is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer.
35. A semiconductor device, comprising:
- a memory array including a plurality of split-gate devices in a memory region of a substrate, each split-gate device including a polysilicon memory gate (MG) overlying a charge trapping layer, and a polysilicon select gate (SG) overlying a SG oxide layer formed adjacent to the MG and separated therefrom by an inter-gate dielectric; and
- control circuitry including a plurality of logic field-effect transistor (FET) in a logic region of the substrate, each logic FET including a metal gate disposed over a high-k dielectric,
- wherein top surfaces of each of the MGs, the SGs and the metal gate of the logic FETs are substantially co-planar.
36. The semiconductor device of claim 35 wherein the inter-gate dielectric in each split gate memory cell extends from the SG oxide layer to the top surfaces of the MG and the SG.
37. The semiconductor device of claim 35 wherein the top surfaces of each of the MG and the SG are silicided, and wherein no silicide lies above the inter-gate dielectric that separates the SG and the MG in each split-gate memory cell.
38. The semiconductor device of claim 35 further comprising an inter-layer dielectric (ILD) formed over the substrate surrounding the MGs, the SGs and the metal gate of the logic FETs, the ILD planarized to have a top surface substantially co-planar with the top surfaces of the MGs, the SGs and the metal gate of the logic FETs.
39. The semiconductor device of claim 35 wherein the charge trapping layer in each split gate memory cell is a multi-layer charge trapping layer comprising an oxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONO stack is formed from an oxide layer that is contiguous with the SG oxide layer.
40. The semiconductor device of claim 35 wherein the control circuitry comprises row and column decoders, sense amplifiers and word line or bit line drivers used to the address plurality of split-gate devices in the memory array.
Type: Application
Filed: Nov 20, 2020
Publication Date: May 6, 2021
Applicant: Cypress Semiconductor Corporation (San Jose, CA)
Inventors: Chun Chen (San Jose, CA), James Pak (Sunnyvale, CA), Unsoon Kim (San Jose, CA), Inkuk Kang (San Jose, CA), Sung-Taeg Kang (Palo Alto, CA), Kuo Tung Chang (Saratoga, CA)
Application Number: 16/953,643