Patents by Inventor Ippei Kume

Ippei Kume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297531
    Abstract: A method of producing a semiconductor device includes forming, on a semiconductor substrate comprising a first surface on which an insulating layer covering a wiring structure and a first through via passing through the insulating layer are formed and a second surface opposed to, and facing away from, the first surface, a patterned first insulating film comprising at least one opening therethrough on the second surface, forming a through via hole inwardly of the second surface within which the wiring structure is exposed, by anisotropic dry etching into the second surface side of the semiconductor substrate through the at least one opening in the first insulating film, using a gas mixture containing SF6, O2, SiF4, and at least one of CF4, Cl2, BCl3, CF3I, and HBr, and forming a second through via in the through via hole.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Noda, Ippei Kume, Kazuhiko Nakamura, Koichi Sato
  • Publication number: 20190139908
    Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
  • Patent number: 10269748
    Abstract: A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ippei Kume, Kengo Uchida
  • Patent number: 10211165
    Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: February 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
  • Patent number: 10204862
    Abstract: A semiconductor device includes a semiconductor substrate provided with a through-hole, a device layer including a lower layer wiring, an insulating layer that covers the device layer, a first through-electrode that passes through the insulating layer, a first insulating film provided with an opening having a diameter that is substantially the same as or greater than an opening diameter of the through-hole of the semiconductor substrate, a second insulating film positioned on an upper side of the first insulating film and on an inner side surface of the through-hole of the semiconductor substrate, and a second through-electrode electrically connected to the lower layer wiring in the device layer from an upper side of the second insulating film through the inside of the through-hole of the semiconductor substrate.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ippei Kume, Kengo Uchida
  • Patent number: 10153227
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 ?m or less.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ippei Kume, Taketo Matsuda, Shinya Okuda, Masahiko Murano
  • Publication number: 20180286783
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 ?m or less.
    Type: Application
    Filed: September 4, 2017
    Publication date: October 4, 2018
    Inventors: Ippei KUME, Taketo MATSUDA, Shinya OKUDA, Masahiko MURANO
  • Publication number: 20180286782
    Abstract: A method of producing a semiconductor device includes forming, on a semiconductor substrate comprising a first surface on which an insulating layer covering a wiring structure and a first through via passing through the insulating layer are formed and a second surface opposed to, and facing away from, the first surface, a patterned first insulating film comprising at least one opening therethrough on the second surface, forming a through via hole inwardly of the second surface within which the wiring structure is exposed, by anisotropic dry etching into the second surface side of the semiconductor substrate through the at least one opening in the first insulating film, using a gas mixture containing SF6, O2, SiF4, and at least one of CF4, Cl2, BCl3, CF3I, and HBr, and forming a second through via in the through via hole.
    Type: Application
    Filed: September 4, 2017
    Publication date: October 4, 2018
    Inventors: Yuki NODA, Ippei KUME, Kazuhiko NAKAMURA, Koichi SATO
  • Publication number: 20180277516
    Abstract: A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. A first metal electrode is between the first and second surface to penetrate through the first substrate and to be connected to the first inductor. The second chip includes a second element provided on a third surface of a second substrate. A second inductor provided above a third surface of the second substrate or a fourth surface located on an opposite side to the third surface. A second metal electrode is provided between the third surface and the fourth surface to penetrate through the second substrate and to be connected to the second inductor. The first and second chips are stacked. The first and second inductors are electrically connected via the first or second metal electrode, as one inductor.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Ippei KUME
  • Publication number: 20180277493
    Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.
    Type: Application
    Filed: September 4, 2017
    Publication date: September 27, 2018
    Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
  • Publication number: 20180269133
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate including a first face having semiconductor elements, and a second face on an opposite side to the first face. A first insulating film is located on the first face of the semiconductor substrate. A conductor is located on the first insulating film. A metal electrode is located between the first face and the second face and passes through the semiconductor substrate to be in contact with the conductor. A second insulating film is located between the metal electrode and the semiconductor substrate. A boundary face between the first insulating film and the second insulating film is located on a side of the conductor relative to the first face of the semiconductor substrate and is inclined to approach the conductor toward a center portion of the metal electrode.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 20, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ippei KUME, Kazuhiko Nakamura, Yuki Noda
  • Patent number: 10026715
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ippei Kume, Kazuyuki Higashi
  • Patent number: 9589951
    Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume
  • Publication number: 20160351521
    Abstract: A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.
    Type: Application
    Filed: March 4, 2016
    Publication date: December 1, 2016
    Inventors: Ippei KUME, Kengo UCHIDA
  • Publication number: 20160351503
    Abstract: A semiconductor device includes a semiconductor substrate provided with a through-hole, a device layer including a lower layer wiring, an insulating layer that covers the device layer, a first through-electrode that passes through the insulating layer, a first insulating film provided with an opening having a diameter that is substantially the same as or greater than an opening diameter of the through-hole of the semiconductor substrate, a second insulating film positioned on an upper side of the first insulating film and on an inner side surface of the through-hole of the semiconductor substrate, and a second through-electrode electrically connected to the lower layer wiring in the device layer from an upper side of the second insulating film through the inside of the through-hole of the semiconductor substrate.
    Type: Application
    Filed: March 4, 2016
    Publication date: December 1, 2016
    Inventors: Ippei KUME, Kengo UCHIDA
  • Publication number: 20160276313
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ippei KUME, Kazuyuki HIGASHI
  • Patent number: 9373679
    Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: June 21, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 9337093
    Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: May 10, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Oshida, Ippei Kume, Makoto Ueki, Manabu Iguchi, Naoya Inoue, Takuya Maruyama, Toshiji Taiji, Hirokazu Katsuyama
  • Publication number: 20160079426
    Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Ippei KUME, Hiroshi TAKEDA, Toshiharu NAGUMO, Takashi HASE
  • Publication number: 20160056145
    Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume