Patents by Inventor Ippei Kume
Ippei Kume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160049375Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Inventors: Ippei KUME, Takashi ONIZAWA, Takashi HASE, Shigeru HIRAO, Tadatoshi DANNO
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Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
Patent number: 9231105Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.Type: GrantFiled: August 21, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Hiroshi Takeda, Toshiharu Nagumo, Takashi Hase -
Patent number: 9196731Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.Type: GrantFiled: August 8, 2014Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
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Publication number: 20150060875Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.Type: ApplicationFiled: August 21, 2014Publication date: March 5, 2015Inventors: Ippei Kume, Hiroshi Takeda, Toshiharu Nagumo, Takashi Hase
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Publication number: 20150060942Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.Type: ApplicationFiled: August 8, 2014Publication date: March 5, 2015Inventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
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Patent number: 8946800Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.Type: GrantFiled: August 23, 2012Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
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Publication number: 20150024593Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.Type: ApplicationFiled: August 1, 2014Publication date: January 22, 2015Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
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Patent number: 8810000Abstract: A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.Type: GrantFiled: January 22, 2009Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
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Patent number: 8803285Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.Type: GrantFiled: May 8, 2007Date of Patent: August 12, 2014Assignee: Renesas Electronics CorporationInventors: Hiroto Ohtake, Naoya Inoue, Ippei Kume, Takeshi Toda, Yoshihiro Hayashi
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Patent number: 8759212Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.Type: GrantFiled: May 5, 2011Date of Patent: June 24, 2014Assignee: Renesas Electronics CorporationInventors: Ippei Kume, Jun Kawahara, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 8648441Abstract: A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.Type: GrantFiled: May 12, 2011Date of Patent: February 11, 2014Assignee: Renesas Electronics CorporationInventors: Kenichiro Hijioka, Ippei Kume, Naoya Inoue, Hiroki Shirai, Jun Kawahara, Yoshihiro Hayashi
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Patent number: 8629529Abstract: A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.Type: GrantFiled: December 25, 2007Date of Patent: January 14, 2014Assignee: NEC CorporationInventors: Naoya Inoue, Ippei Kume, Jun Kawahara, Yoshihiro Hayashi
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Patent number: 8624328Abstract: Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.Type: GrantFiled: November 6, 2009Date of Patent: January 7, 2014Assignee: Renesas Electronics CorporationInventors: Jun Kawahara, Yoshihiro Hayashi, Ippei Kume
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Publication number: 20130056850Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.Type: ApplicationFiled: August 23, 2012Publication date: March 7, 2013Inventors: Ippei KUME, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
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Patent number: 8390046Abstract: A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.Type: GrantFiled: November 16, 2010Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Jun Kawahara, Yoshihiro Hayashi, Ippei Kume
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Publication number: 20120015517Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.Type: ApplicationFiled: July 14, 2011Publication date: January 19, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke OSHIDA, Ippei KUME, Makoto UEKI, Manabu IGUCHI, Naoya INOUE, Takuya MARUYAMA, Toshiji TAIJI, Hirokazu KATSUYAMA
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Publication number: 20110284991Abstract: A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.Type: ApplicationFiled: May 12, 2011Publication date: November 24, 2011Inventors: Kenichiro HIJIOKA, Ippei Kume, Naoya Inoue, Hiroki Shirai, Jun Kawahara, Yoshihiro Hayashi
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Publication number: 20110272813Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.Type: ApplicationFiled: May 5, 2011Publication date: November 10, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ippei KUME, Jun KAWAHARA, Naoya FURUTAKE, Shinobu SAITOU, Yoshihiro HAYASHI
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Publication number: 20110121375Abstract: A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.Type: ApplicationFiled: November 16, 2010Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Jun KAWAHARA, Yoshihiro HAYASHI, Ippei KUME
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Publication number: 20100327409Abstract: A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.Type: ApplicationFiled: January 22, 2009Publication date: December 30, 2010Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi