Abstract: A wide bandwidth attenuator input circuit for a measurement probe has a Z0 attenuator circuit coupled in series with a compensated RC attenuator circuit. The series attenuator elements of the Z0 and the compensated RC attenuator circuits are coupled via a controlled impedance transmission line to the shunt attenuator elements of the Z0 and the compensated RC attenuator circuits. The shunt element of the Z0 attenuator element terminates the transmission line in its characteristic impedance. The junction of the series and shunt attenuator elements are coupled to the input of a buffer amplifier. At low and intermediate frequencies, the compensated RC attenuator circuit attenuates an input signal while at high frequencies, the compensated RC attenuator circuit acts as a short and the Z0 attenuator circuits attenuates the input signal.

Abstract: A differential termination and attenuator network having an internal common mode termination voltage generator includes first and second termination resistors coupled in parallel with corresponding resistive attenuator circuits. A monitoring circuit coupled to input nodes of the network generates an output signal representative of the combination of a DC common mode voltage on the input nodes and an internal termination voltage. A control circuit generates scaled termination and compensation voltages and associated drive currents using the internal termination voltage and the monitoring circuit output signal. The scaled termination voltage and the scaled compensation voltage operate on the differential termination and attenuation network to optimize the dynamic range of a differential amplifier connected to the first and second attenuator outputs and null the DC currents at the input of the network.

Abstract: A differential termination and attenuator network receives a differential input signal having a DC common mode voltage. The network circuit includes input termination resistors coupled in parallel with corresponding resistive attenuator circuits. A monitoring circuit coupled to input nodes of the network generates an output signal representative of the combination of a DC common mode voltage on the input nodes and an applied termination voltage. A control circuit receives the output signal from the monitoring circuit and the applied termination voltage and generates a scaled termination voltage and a scaled compensation voltage and drive currents. The scaled termination and compensation voltages and drive currents provide DC currents through the input termination resistances and the attenuators for nulling DC currents at the network input nodes and provides a DC common mode voltage output from the attenuators for optimizing the dynamic range of a differential measurement amplifier.

Abstract: A differential termination and attenuator network having an automated common mode termination voltage generator includes first and second termination resistors coupled in parallel with corresponding resistive attenuator circuits. A monitoring circuit coupled to input nodes of the network generates an output signal representative of the combination of a DC common mode voltage on the input nodes and an adjustable termination voltage. A control circuit generates scaled termination and compensation voltages and associated drive currents using the adjustable termination voltage and the monitoring circuit output signal. The scaled termination voltage and the scaled compensation voltage operate on the differential termination and attenuation network to optimize the dynamic range of a differential amplifier connected to the first and second attenuator outputs.

Abstract: A attachable/detachable probing tip system (10) has a housing (12) that includes a probing tip mounting member (14) and opposing substantially orthogonal attachment (16, 18) arms extending from the probing tip mounting member. The attachment arms define an inner surface of the probing tip mounting member in which is disposed at least a first a non-compressive set, resilient member (56). First and second probing tips (42, 44) are disposed over the non-compressive, resilient member (56) and secured to the housing by latching means (60, 66, 92, 96, 100, 130). The attachable/detachable probing tip system allows mounting of the probing tips (42, 44) to probing contacts on a device under test without a probe body or probing tip member (38) being attached. The attachment arms (16, 18) allows a probe body or probing tip member (38) to be attached and detached to the probing tip system (10). The probing tip member (38) includes contact pins that engage contact areas (82, 82, 92) of the probing tips (42, 44).

Abstract: A user interface for a tester or simulator includes a menu for creating templates. The templates organize a set of the user's decisions regarding the timing, direction, and masking of all of the signals occurring during one tester cycle into a convenient form for use in another menu where test vectors are actually specified. In this other menu, the templates serve as a shorthand way of describing the function of each channel and its timing characteristics during one tester cycle. Thus, these templates organize and simplify the user's decision making, since many decisions, that would otherwise have to be made again and again, may now be made only once and then incorporated again and again by reference to the appropriate template. The use of the templates also conserves total memory requirements. The template menu can provide visual feedback that includes timing diagrams and icons to assist the user in constructing the template.

Abstract: A multiple digital event generator produces events with timing that is programmable, yet the event generator requires a minimum of circuitry for its construction and is capable of operating at very high speeds. A linear feedback shift register is used to produce an arbitrary sequence of non-repeating binary numbers. These numbers are then monitored by one or more digital comparators whose other digital input is chosen so as to cause the desired event to occur when a certain number in the number sequence occurs. The minimum time between events and the maximum range of event control timing is adjustable by varying the frequency of the clock input to the linear feedback shift register. Maximum speed is achieved by using one set of the shift register flip-flop outputs (Q or Q-not) for internal feedback and the other set (Q-not or Q) for the output to the digital comparators, so that the speed of operation of the shift register is not degraded by the load of the multiple digital comparator circuits on its output.

Abstract: A probe for coupling electrical test equipment to a selected point of an electrical device has a resiliently supported rigid pin for contacting the selected point and a wave guide of substantially constant characteristic impedance coupling the test equipment to the pin.

Abstract: A supergate having an enabled differential input, a single ended input and a differential output provides high speed communication between electronic cards in an electronic device. The enabled differential input is input to a differential amplifier which is electrically driven by a current source. A differential AND gate having the single ended input as an input is electrically driven by one output of the differential amplifier and provides the differential output. The other output of the differential amplifier is OR'd with one side of the differential output so that the propagation delay for the enabled differential input is essentially the same as that for the single ended input. Current steering is used to provide high speed signal flow through the differential amplifier and the differential AND gate.

Abstract: A propagation delay time controller comprises a phase locked ring oscillator and a bias signal generator for controlling the propagation delay time of logic elements on an integrated circuit. The logic elements are of a type in which propagation delay time is a function of an applied bias signal. The ring oscillator, comprising representative logic elements on the controlled integrated circuit, oscillates with a frequency dependent on the propagation delay time of the oscillator logic elements. The bias signal generator compares the oscillator output voltage with a known, pulsed reference signal and generates a bias signal proportional to the integral of the phase difference between the oscillator and reference signal pulses. The bias signal is applied to all logic elements in the ring oscillator and to all other logic elements on the integrated circuit to be controlled.