Patents by Inventor Iris Moder

Iris Moder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176580
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Publication number: 20200168449
    Abstract: A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10?2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 28, 2020
    Inventors: Sophia Friedler, Bernhard Goller, Iris Moder, Ingo Muri
  • Publication number: 20200098617
    Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10535553
    Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10497583
    Abstract: According to embodiments, a method for manufacturing a semiconductor device includes forming a mask comprising a pattern of inert structures on a side of a first main surface of a semiconductor substrate. A semiconductor layer is formed over the first main surface, and the semiconductor substrate is thinned from a second main surface opposite to the first main surface. Thereafter, a semiconductor region laterally adjoining the inert structures is anisotropically etched.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 3, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Sophia Friedler, Ingo Muri, Hans-Joachim Schulze
  • Publication number: 20190348506
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Patent number: 10325804
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20190074212
    Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Inventors: Ingo Muri, Bernhard Goller, Iris Moder, Hans-Joachim Schulze
  • Patent number: 10199372
    Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Iris Moder, Oliver Hellmund, Johannes Baumgartl, Annette Saenger, Barbara Eichinger, Doris Sommer, Jacob Tillmann Ludwig
  • Publication number: 20180374843
    Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: Ingo Muri, Iris Moder, Oliver Hellmund, Johannes Baumgartl, Annette Saenger, Barbara Eichinger, Doris Sommer, Jacob Tillmann Ludwig
  • Publication number: 20180330981
    Abstract: According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 15, 2018
    Inventors: Roland Rupp, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Iris Moder, Ingo Muri
  • Publication number: 20180277391
    Abstract: According to embodiments, a method for manufacturing a semiconductor device includes forming a mask comprising a pattern of inert structures on a side of a first main surface of a semiconductor substrate. A semiconductor layer is formed over the first main surface, and the semiconductor substrate is thinned from a second main surface opposite to the first main surface. Thereafter, a semiconductor region laterally adjoining the inert structures is anisotropically etched.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 27, 2018
    Inventors: Iris Moder, Sophia Friedler, Ingo Muri, Hans-Joachim Schulze
  • Publication number: 20180267408
    Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Inventors: Joerg Ortner, Iris Moder, Ingo Muri
  • Patent number: 10074566
    Abstract: A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johannes Baumgartl, Manfred Engelhardt, Oliver Hellmund, Iris Moder, Ingo Muri
  • Publication number: 20180233399
    Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10049914
    Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Hans-Joachim Schulze, Francisco Javier Santos Rodriguez, Iris Moder, Ingo Muri
  • Publication number: 20180144974
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 24, 2018
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20180144982
    Abstract: A method is disclosed for use in manufacturing semiconductor dice. The method comprises providing a wafer substrate that comprises dicing areas, providing a first etch stop material outside the dicing areas, and etching the wafer substrate down to the first etch stop material. A semiconductor device chip is also disclosed. The semiconductor device chip comprises a device layer comprising a semiconductor device and a metal support layer supporting the device layer. The metal support layer provides a metal side wall protection of the device layer.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 24, 2018
    Inventors: Ingo Muri, Oliver Hellmund, Iris Moder, Hans-Joachim Schulze
  • Patent number: 9960076
    Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 9954065
    Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Ingo Muri, Iris Moder, Johannes Baumgartl