Patents by Inventor Irwin Yablok

Irwin Yablok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9691632
    Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 27, 2017
    Assignees: Siltronic AG, Intel Corporation
    Inventors: Peter Storck, Norbert Werner, Martin Vorderwestner, Peter Tolchinsky, Irwin Yablok
  • Publication number: 20150303071
    Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.
    Type: Application
    Filed: December 3, 2013
    Publication date: October 22, 2015
    Inventors: Peter STORCK, Norbert WERNER, Martin VORDERWESTNER, Peter TOLCHINSKY, Irwin YABLOK
  • Publication number: 20100155880
    Abstract: A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×1017 cm?3, a nitrogen layer adjacent to the back gate region of the base silicon substrate, a BOX layer adjacent to the nitrogen layer, and a thin silicon device layer adjacent to the BOX layer, wherein the thin silicon device layer has a first dopant concentration that is less than 1×1017 cm?3. In some implementations, the thin silicon device layer has a first dopant concentration that is less than 1×1015 cm?3.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Ibrahim Ban, Peter G. Tolchinsky, Irwin Yablok
  • Patent number: 7531429
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard D. Emery
  • Publication number: 20090096025
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2008
    Publication date: April 16, 2009
    Inventors: Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad Shaheen, Irwin Yablok
  • Patent number: 7491988
    Abstract: A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Mark Bohr, Irwin Yablok
  • Patent number: 7473614
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad Shaheen, Irwin Yablok
  • Publication number: 20080122042
    Abstract: A wafer comprising polycrystalline silicon is used in various applications, including as a handling wafer, a test wafer, a dummy wafer, or as a substrate in a bonded die. Use of polycrystalline material instead of single-crystal may lower expenses.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Inventors: Michael Goldstein, Irwin Yablok
  • Patent number: 7378331
    Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Mohamad Shaheen, Peter G. Tolchinsky, Irwin Yablok, Scott R. List
  • Publication number: 20070063279
    Abstract: A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Inventors: Peter Tolchinsky, Mohamad Shaheen, Martin Giles, Irwin Yablok, Aaron Budrevich
  • Patent number: 7161224
    Abstract: More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Mohamad Shaheen, Ryan Lei, Irwin Yablok
  • Patent number: 7091108
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard D. Emery
  • Publication number: 20060177994
    Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
    Type: Application
    Filed: April 3, 2006
    Publication date: August 10, 2006
    Inventors: Peter Tolchinsky, Irwin Yablok, Chuan Hu, Richard Emery
  • Publication number: 20060138627
    Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventors: Mohamad Shaheen, Peter Tolchinsky, Irwin Yablok, Scott List
  • Publication number: 20060102988
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Inventors: Peter Tolchinsky, Martin Giles, Michael McSwiney, Mohamad Shaheen, Irwin Yablok
  • Publication number: 20050285212
    Abstract: A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Peter Tolchinsky, Mark Bohr, Irwin Yablok
  • Publication number: 20050217560
    Abstract: The crystal orientations of monocrystalline semiconductor wafers may be varied by four parameters. The first parameter is the type of crystal seed used to grow the monocrystalline semiconductor ingot from which the wafers are cut. The second parameter is the angle at which the wafer is sliced from the ingot. The third parameter is the crystal plane towards which the wafer is cut. And, the fourth parameter is the position of the orientation indication feature that is used to align the wafer during processing. Different combinations of these parameters provide variations of non-standard crystal orientations of monocrystalline semiconductor wafers and semiconductor-on-insulator substrates such as silicon-on-insulator.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Peter Tolchinsky, Mohamad Shaheen, Irwin Yablok
  • Publication number: 20050173781
    Abstract: More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 11, 2005
    Inventors: Peter Tolchinsky, Mohamad Shaheen, Ryan Lei, Irwin Yablok
  • Patent number: 6924543
    Abstract: A method and apparatus for a semiconductor device having increased electrical carrier mobility is described. That method and apparatus comprises forming two recesses within a substrate, and providing a material within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses. Also described is a semiconductor device that comprises a substrate having two recesses formed therein, and a material disposed within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Irwin Yablok
  • Patent number: 6911380
    Abstract: A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Irwin Yablok, Mohamad A. Shaheen