Patents by Inventor Isaac Lauer

Isaac Lauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220123449
    Abstract: Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Inventors: Isaac Lauer, William Francis Landers, Srikanth Srinivasan, Neereja Sundaresan
  • Publication number: 20220102613
    Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Isaac Lauer, Karthik Balakrishnan, Jeffrey Sleight, David James Frank
  • Publication number: 20220102612
    Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Isaac Lauer, Karthik Balakrishnan, Jeffrey Sleight, David James Frank
  • Publication number: 20220093772
    Abstract: A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
  • Publication number: 20220028927
    Abstract: Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles. In various embodiments, the qubit lattice can exhibit a rectilinear physical layout. In various embodiments, the one or more first qubit tiles tessellated with the one or more second qubit tiles can form a heavy-hex qubit connection topology in the rectilinear physical layout of the qubit lattice.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Isaac Lauer, Neereja Sundaresan
  • Publication number: 20220019927
    Abstract: Systems and techniques that facilitate qubit pulse calibration via canary parameter monitoring are provided. In various embodiments, a system can comprise a measurement component that can measure a canary parameter associated with a qubit control channel. In various embodiments, the system can further comprise a scaling component that can modify a plurality of parameters associated with the qubit control channel via a scaling factor. In various cases, the scaling factor can be based on the canary parameter. In various embodiments, the canary parameter can be a rotation error of a qubit driven by a microwave pulse transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be amplitudes of a plurality of microwave pulses transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be phases of a plurality of microwave pulses transmitted along the qubit control channel.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 20, 2022
    Inventor: Isaac Lauer
  • Patent number: 11223347
    Abstract: Techniques facilitating dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum coupling device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using off-resonant microwave signals applied via the respective first and second drive lines.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David C. Mckay, Abhinav Kandala, Oliver Dial, Matthias Steffen, Isaac Lauer
  • Publication number: 20210342161
    Abstract: Techniques regarding resetting highly excited qubits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a reset component that can de-excite a qubit system to a target state by transitioning a population of a first excited state of the qubit system to a ground state and by applying a signal to the qubit system that transitions a population of a second excited state to the first excited state.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Inventors: Isaac Lauer, Oliver Dial, Matthias Steffen
  • Publication number: 20210280674
    Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Publication number: 20210258079
    Abstract: Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Isaac Lauer, Neereja Sundaresan
  • Patent number: 11069775
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11004933
    Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 11, 2021
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11004678
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10699955
    Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10680061
    Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10658461
    Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Publication number: 20200091289
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10580894
    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20200066508
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10573714
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao