Patents by Inventor Isaac Lauer

Isaac Lauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-replacement gate nanomesh field effect transistor with pad regions
    Patent number: 8900959
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Diode structure for gate all around silicon nanowire technologies
    Patent number: 8901655
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Gate stack including a high-K gate dielectric that is optimized for low voltage applications
    Patent number: 8901616
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES
    Publication number: 20140339639
    Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • STRINGER-FREE GATE ELECTRODE FOR A SUSPENDED SEMICONDUCTOR FIN
    Publication number: 20140332890
    Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.
    Type: Application
    Filed: September 11, 2013
    Publication date: November 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • STRINGER-FREE GATE ELECTRODE FOR A SUSPENDED SEMICONDUCTOR FIN
    Publication number: 20140332892
    Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey N. Sleight
  • Semiconductor device including an asymmetric feature, and method of making the same
    Patent number: 8877593
    Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.
    Type: Grant
    Filed: July 31, 2011
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
  • Multi-direction wiring for replacement gate lines
    Patent number: 8872241
    Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
    Patent number: 8872274
    Abstract: An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy M Cohen, David J Frank, Isaac Lauer
  • SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT
    Publication number: 20140312397
    Abstract: A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.
    Type: Application
    Filed: September 16, 2013
    Publication date: October 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-bang Yau
  • SELF-ALIGNED BORDERLESS CONTACTS USING A PHOTO-PATTERNABLE DIELECTRIC MATERIAL AS A REPLACEMENT CONTACT
    Publication number: 20140312395
    Abstract: A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Szu-lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-bang Yau
  • Multi-direction wiring for replacement gate lines
    Patent number: 8865531
    Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
    Patent number: 8859410
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Semiconductor nanowire structure reusing suspension pads
    Patent number: 8853790
    Abstract: An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • GATE STACK OF BORON SEMICONDUCTOR ALLOY, POLYSILICON AND HIGH-K GATE DIELECTRIC FOR LOW VOLTAGE APPLICATIONS
    Publication number: 20140264638
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS
    Publication number: 20140264276
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • GATE STACK OF BORON SEMICONDUCTOR ALLOY, POLYSILICON AND HIGH-K GATE DIELECTRIC FOR LOW VOLTAGE APPLICATIONS
    Publication number: 20140264639
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Application
    Filed: September 18, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS
    Publication number: 20140252493
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS
    Publication number: 20140252492
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE
    Publication number: 20140252501
    Abstract: At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening.
    Type: Application
    Filed: September 12, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-Bang Yau