Abstract: A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Abstract: A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion.

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

Abstract: A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench. The patterns in the arrays of polymer lines are transferred into an underlying material layer to form arrays of patterned material structures. The arrays of patterned material structures may be arrays of semiconductor material portion, or may be arrays of gate electrodes. An array of patterned material structures may be at a non-orthogonal angle with respect to an array of underlying material portions or with respect to an array of overlying material portions to be subsequently formed.

Abstract: A template material layer is deposited over a substrate, and is patterned with at least two trenches having different lengthwise directions. An array of polymer lines are formed by directed self-assembly of a copolymer material and a selective removal of one type of polymer material relative to another type within each trench such that the lengthwise direction of the polymer lines are parallel to the lengthwise sidewalls of the trench. The patterns in the arrays of polymer lines are transferred into an underlying material layer to form arrays of patterned material structures. The arrays of patterned material structures may be arrays of semiconductor material portion, or may be arrays of gate electrodes. An array of patterned material structures may be at a non-orthogonal angle with respect to an array of underlying material portions or with respect to an array of overlying material portions to be subsequently formed.

Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.

Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.

Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.