Patents by Inventor Isaho Kamata
Isaho Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120325138Abstract: A film-forming apparatus and method comprising a film-forming chamber for supplying a reaction gas into, a cylindrical shaped liner provided between an inner wall of the film-forming chamber and a space for performing a film-forming process, a main-heater for heating a substrate placed inside the liner, from the bottom side, a sub-heater cluster provided between the liner and the inner wall, for heating the substrate from the top side, wherein the main-heater and the sub-heater cluster are resistive heaters, wherein the sub-heater cluster has a first sub-heater provided at the closest position to the substrate, and a second sub-heater provided above the first sub-heater, wherein the first sub-heater heats the substrate in combination with the main-heater, the second sub-heater heats the liner at a lower output than the first sub-heater, wherein each temperature of the main-heater, the first sub-heater, and the second sub-heater is individually controlled.Type: ApplicationFiled: June 19, 2012Publication date: December 27, 2012Applicants: NuFlare Techology, Inc., Toyota Jidosha Kabushiki Kaisha, Denso Corporation, Central Res. Institute of Electric Power IndustryInventors: Kunihiko SUZUKI, Hideki Ito, Naohisa Ikeya, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito, Masami Naito, Hiroaki Fujibayashi, Ayumu Adachi, Koichi Nishikawa
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Patent number: 8293623Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.Type: GrantFiled: September 12, 2008Date of Patent: October 23, 2012Assignees: Showa Denko K.K., National Institute of Advanced Industrial Science and Technology, Central Research Institute of Electric Power IndustryInventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
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Patent number: 8154026Abstract: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage.Type: GrantFiled: December 13, 2006Date of Patent: April 10, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Tomonori Nakamura
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Patent number: 7960738Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960257Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960737Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20110006309Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.Type: ApplicationFiled: September 12, 2008Publication date: January 13, 2011Applicant: SHOWA DENKO K.K.Inventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
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Publication number: 20100261333Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100258816Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Joji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100258817Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7768017Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: December 1, 2004Date of Patent: August 3, 2010Assignees: The Kansai Electric Co., Inc., Central Research Institution of Electrical Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20090317983Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.Type: ApplicationFiled: September 1, 2006Publication date: December 24, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20090195296Abstract: In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.Type: ApplicationFiled: August 4, 2006Publication date: August 6, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20090045413Abstract: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage.Type: ApplicationFiled: December 13, 2006Publication date: February 19, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Tomonori Nakamura
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Publication number: 20070290211Abstract: A process for manufacturing a bipolar type semiconductor device in which at least a part of a region where an electron and a hole are recombined during current flowing is formed with a silicon carbide epitaxial layer that has been grown from the surface of a silicon carbide substrate, is characterized by that the surface of the silicon carbide substrate is treated by hydrogen etching and the epitaxial layer is then formed by the epitaxial growth of silicon carbide from the treated surface. A propagation of a basal plane dislocation to the epitaxial layer can be further reduced by treating the surface of the silicon carbide substrate by using chemical mechanical polishing and hydrogen etching in this order.Type: ApplicationFiled: March 25, 2005Publication date: December 20, 2007Applicants: The Kansai Electric Power Co., Inc., Cental Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20070090370Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: December 1, 2004Publication date: April 26, 2007Inventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7081420Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burghers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.Type: GrantFiled: March 19, 2003Date of Patent: July 25, 2006Assignee: Central Research Institute of Electric Power IndustryInventors: Isaho Kamata, Hidekazu Tsuchida
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Publication number: 20050181627Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burgers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.Type: ApplicationFiled: March 19, 2003Publication date: August 18, 2005Inventors: Isaho Kamata, Hidekazu Tsuchida