Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: In a partial display mode, a source IC outputs a start signal at an “H” level designating the start of vertical scanning by a vertical scanning circuit, over a plurality of cycles from before a time T1 to after a time T8. A plurality of shift registers sequentially shift the start signal in synchronization with a clock signal to sequentially drive a plurality of activation enable signals, respectively, to an “H” level. Then, after time T8 when first to fourth activation enable signals simultaneously attain an “H” level, the source IC outputs an enabling signal at an “H” level to the vertical scanning circuit. In response, the vertical scanning circuit simultaneously activates first to fourth gate lines corresponding to the first to the fourth activation enable signals, respectively.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: An image display device includes a liquid crystal display part, a gate line driving circuit, a source line driving circuit, and a timing controller. The source line driving circuit includes a horizontal shift register, a first latch circuit, a second latch circuit, a D/A converter circuit, and a demultiplexer capable of driving a plurality of source lines divided into a plurality of batches. The timing controller includes a pulse generating circuit, a signal transmission circuit, and a shift pulse generating circuit for generating a second latch signal and for sending a shifted start signal back to the signal transmission circuit.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: A protection circuit described herein protects an LCD module from static electricity generated at a first positive power supply terminal in a process of manufacturing the LCD module. The protection circuit includes four diodes connected in series between a first node connected to the first positive power supply terminal and a second node receiving a reference potential, and a diode connected between the second and first nodes. When a first positive power supply voltage (10V) is applied to the first positive power supply terminal, the four diodes do not conduct. Therefore, a current consumption of the LCD module can accurately be measured.

Abstract: An LCD module includes: an odd-numbered data terminal for applying an odd-numbered data signal to each odd-numbered set of data lines through a first N-type TFT and a demultiplexer at inspection; an even-numbered data terminal for applying an even-numbered data signal to each even-numbered set of data lines through a second N-type TFT and the demultiplexer at inspection; and a control terminal for applying a control signal to gates of the first and second N-type TFTs at inspection. It is therefore possible to reduce the number of terminals to be used at inspection, thereby achieving a inspection device at low cost.

Abstract: A liquid crystal display unit is divided into a plurality of blocks aligned in a horizontal direction. Each block has twenty-four source lines. A plurality of data buses are arranged corresponding to the plurality of blocks, respectively. Each data bus receives image data from a data terminal. Each data bus is arranged without crossing the other data buses. Each block receives the image data from the one data bus.

Abstract: In a partial display mode, a source IC outputs a start signal at an “H” level designating the start of vertical scanning by a vertical scanning circuit, over a plurality of cycles from before a time T1 to after a time T8. A plurality of shift registers sequentially shift the start signal in synchronization with a clock signal to sequentially drive a plurality of activation enable signals, respectively, to an “H” level. Then, after time T8 when first to fourth activation enable signals simultaneously attain an “H” level, the source IC outputs an enabling signal at an “H” level to the vertical scanning circuit. In response, the vertical scanning circuit simultaneously activates first to fourth gate lines corresponding to the first to the fourth activation enable signals, respectively.

Abstract: An LCD module includes: an odd-numbered data terminal for applying an odd-numbered data signal to each odd-numbered set of data lines through a first N-type TFT and a demultiplexer at inspection; an even-numbered data terminal for applying an even-numbered data signal to each even-numbered set of data lines through a second N-type TFT and the demultiplexer at inspection; and a control terminal for applying a control signal to gates of the first and second N-type TFTs at inspection. It is therefore possible to reduce the number of terminals to be used at inspection, thereby achieving a inspection device at low cost.

Abstract: A protection circuit described herein protects an LCD module from static electricity generated at a first positive power supply terminal in a process of manufacturing the LCD module. The protection circuit includes four diodes connected in series between a first node connected to the first positive power supply terminal and a second node receiving a reference potential, and a diode connected between the second and first nodes. When a first positive power supply voltage (10V) is applied to the first positive power supply terminal, the four diodes do not conduct. Therefore, a current consumption of the LCD module can accurately be measured.

Abstract: In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.

Abstract: In the non-volatile semiconductor memory device, for a current mirror for reading out data of a memory cell, a diode-connected transistor and a cut transistor are provided. The diode-connected transistor makes a precharged voltage level lower than a power supply voltage level. The cut transistor reduces current consumption.

Abstract: A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference between the reference current and the memory cell current at the first node and an output level setting part for generating an output signal,at the second node. The output level setting part has the first transistor for supplying a constant current in accordance with the control voltage from the power supply node to the second node and the second transistor for allowing the current in accordance with the voltage of the node to flow from the second node to the ground node. The current which flows through the second transistor is designed to be in balance with the constant current under the condition where the reference current and the memory cell current are in balance.

Abstract: A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference between the reference current and the memory cell current at the first node and an output level setting part for generating an output signal at the second node. The output level setting part has the first transistor for supplying a constant current in accordance with the control voltage from the power supply node to the second node and the second transistor for allowing the current in accordance with the voltage of the node to flow from the second node to the ground node. The current which flows through the second transistor is designed to be in balance with the constant current under the condition where the reference current and the memory cell current are in balance.

Abstract: In the non-volatile semiconductor memory device, for a current mirror for reading out data of a memory cell, a diode-connected transistor and a cut transistor are provided. The diode-connected transistor makes a precharged voltage level lower than a power supply voltage level. The cut transistor reduces current consumption.

Abstract: In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.