Patents by Inventor Isao Nojiri

Isao Nojiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6263717
    Abstract: A press-forming die set including a first die and a second die which are linearly movable in a press-forming direction for mutual engagement to form a negative-angle portion on a workpiece placed on the second die, the press-forming die further including a rotary cam having a first negative-angle forming portion, and a forming cam having a second negative-angle forming portion. The first negative-angle forming portion is disposed such that the rotary cam is rotatable about an axis of rotation inclined with respect to a bottom surface of the workpiece. The rotary cam is engageable with the second die and is rotated about the axis of rotation in one of opposite directions when the first and second dies are moved toward each other, and is rotated in the other direction when the first and second dies are moved away from each other.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: July 24, 2001
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Isao Nojiri
  • Patent number: 5257224
    Abstract: A plurality of strip shaped first polysilicon layers 3 are formed on a monocrystalline silicon substrate 1, a plurality of strip shaped second polysilicon layers 5 are formed thereon crossing the first polysilicon layers 3, and a plurality of strip shaped third polysilicon layers 8 are further formed thereon crossing the second polysilicon layers 5. The first and second polysilicon layers 3 and 5 are laser-annealed and monocrystallined. Contact holes 4 and 7 are selectively formed at the crossing points of the first polysilicon layers 3 and the second polysilicon layers 5, and the crossing points of the second polysilicon layers 5 and the third polysilicon layers 8. A PN junction is formed on each surface layer of the first polysilicon layers 3 and the second polysilicon layers 5 in the portions corresponding to these contact holes 4 and 7. Two layers of memory cell arrays using diode elements as memory cells are piled upon each other.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: October 26, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Isao Nojiri, Masahide Kaneko