Patents by Inventor Islam Salama

Islam Salama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11430740
    Abstract: Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Kristof Darmawikarta, Robert L. Sankman, Amruthavalli Pallavi Alur
  • Publication number: 20220230965
    Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Inventors: Robert Alan MAY, Islam A. SALAMA, Sri Ranga Sai BOYAPATI, Sheng LI, Kristof DARMAWIKARTA, Robert L. SANKMAN, Amruthavalli Pallavi ALUR
  • Publication number: 20220108957
    Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Robert Alan MAY, Islam A. SALAMA, Sri Ranga Sai BOYAPATI, Sheng LI, Kristof DARMAWIKARTA, Robert L. SANKMAN, Amruthavalli Pallavi ALUR
  • Publication number: 20210280517
    Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 9, 2021
    Inventors: Robert Alan May, Wei-Lun Kane Jen, Jonathan L. Rosch, Islam A. Salama, Kristof Darmawikarta
  • Publication number: 20210257303
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Amruthavalli Pallavi ALUR, Sri Ranga Sai BOYAPATI, Robert Alan MAY, Islam A. SALAMA, Robert L. SANKMAN
  • Patent number: 11043457
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Publication number: 20200303310
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 24, 2020
    Inventors: Amruthavalli Pallavi ALUR, Sri Ranga Sai BOYAPATI, Robert Alan MAY, Islam A. SALAMA, Robert L. SANKMAN
  • Publication number: 20200294920
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Haifa HARIRI, Amruthavalli P. ALUR, Wei-Lun K. JEN, Islam A. SALAMA
  • Publication number: 20200294938
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Rahul JAIN, Kyu-Oh LEE, Islam A. SALAMA, Amruthavalli P. ALUR, Wei-Lun K. JEN, Yongki MIN, Sheng C. LI
  • Patent number: 10707168
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Patent number: 10553453
    Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Chavali, Siddharth K. Alur, Amanda E. Schuckman, Amruthavalli Palla Alur, Islam A. Salama, Yikang Deng, Kristof Darmawikarta
  • Publication number: 20190341351
    Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
    Type: Application
    Filed: March 29, 2017
    Publication date: November 7, 2019
    Inventors: Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Kristof Darmawikarta, Robert L. Sankman, Amruthavalli Pallavi Alur
  • Publication number: 20190311916
    Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.
    Type: Application
    Filed: July 14, 2016
    Publication date: October 10, 2019
    Inventors: Sri Chaitra CHAVALI, Siddharth K. ALUR, Amanda E. SCHUCKMAN, Amruthavalli Palla ALUR, Islam A. SALAMA, Yikang DENG, Kristof DARMAWIKARTA
  • Patent number: 10424561
    Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20190198445
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 27, 2019
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Patent number: 10306760
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 10286488
    Abstract: Embodiments of the present disclosure are directed towards an acousto-optics deflector and mirror for laser beam steering and associated techniques and configurations. In one embodiment, a laser system may include an acousto-optics module to deflect a laser beam in a first scanning direction of the laser beam on an integrated circuit (IC) substrate when the IC substrate is in a path of the laser beam and a mirror having at least one surface to receive the laser beam from the acousto-optics module, the mirror to move to control position of the laser beam in a second scanning direction, wherein the second scanning direction is substantially perpendicular to the first scanning direction. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 14, 2019
    Assignee: INTEL CORPORATION
    Inventors: Chong Zhang, Islam A. Salama
  • Patent number: 10163798
    Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Amruthavalli Pallavi Alur, Sri Ranga Sai Boyapati, Robert Alan May, Islam A. Salama, Robert L. Sankman
  • Publication number: 20180226381
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: January 5, 2018
    Publication date: August 9, 2018
    Inventors: KYU-OH LEE, ISLAM A. SALAMA, RAM S. VISWANATH, ROBERT L. SANKMAN, BABAK SABI, SRI CHAITRA JYOTSNA CHAVALI
  • Patent number: 10043740
    Abstract: Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Coporation
    Inventors: Sri Ranga Sai Boyapati, Rahul N. Manepalli, Dilan Seneviratne, Srinivas V. Pietambaram, Kristof Darmawikarta, Robert Alan May, Islam A. Salama