Patents by Inventor Islam Salama

Islam Salama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170036301
    Abstract: Embodiments of the present disclosure are directed towards an acousto-optics deflector and mirror for laser beam steering and associated techniques and configurations. In one embodiment, a laser system may include an acousto-optics module to deflect a laser beam in a first scanning direction of the laser beam on an integrated circuit (IC) substrate when the IC substrate is in a path of the laser beam and a mirror having at least one surface to receive the laser beam from the acousto -optics module, the mirror to move to control position of the laser beam in a second scanning direction, wherein the second scanning direction is substantially perpendicular to the first scanning direction. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 9, 2017
    Inventors: Chong Zhang, Islam A. Salama
  • Patent number: 9505607
    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Kyu Oh Lee, Zheng Zhou, Islam A. Salama, Feras Eid, Sasha N. Oster, Lay Wai Kong, Javier Soto Gonzalez
  • Publication number: 20160302307
    Abstract: A method of providing a printed circuit board, a printed circuit board formed according to the method, and a system comprising the printed circuit board. The method comprises: providing a microelectronic substrate; providing a via-defining substrate by providing via openings in the substrate using laser irradiation; providing a laser activatable film on the via-defining substrate; and providing interconnects on the via-defining substrate. Providing interconnects comprises providing a patterned build-up layer on the via-defining substrate comprising exposing the laser activatable film to laser irradiation to selectively activate portions of the film according to a predetermined interconnect pattern; and metallizing the patterned build-up layer according to the predetermined interconnect pattern to yield the interconnects to provide the printed circuit board.
    Type: Application
    Filed: June 19, 2007
    Publication date: October 13, 2016
    Inventor: Islam A. Salama
  • Publication number: 20160300824
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 13, 2016
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Publication number: 20160280535
    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: Kyu Oh Lee, Zheng Zhou, Islam A. Salama, Feras Eid, Sasha N. Oster, Lay Wai Kong, Javier Soto Gonzalez
  • Publication number: 20160274857
    Abstract: Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.
    Type: Application
    Filed: June 2, 2016
    Publication date: September 22, 2016
    Inventors: Johanna M. Swan, Uygar Avci, Islam A. Salama, Ravi Pillarisetty
  • Patent number: 9442286
    Abstract: A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam A. Salama, Chong Zhang
  • Patent number: 9397071
    Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, John S. Guzek, Johanna M. Swan, Christopher J. Nelson, Nitin A. Deshpande, William J. Lambert, Charles A. Gealer, Feras Eid, Islam A. Salama, Kemal Aygun, Sasha N. Oster, Tyler N. Osborn
  • Patent number: 9361059
    Abstract: Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Johanna Swan, Uygar Avci, Islam A. Salama, Ravi Pallarisetty
  • Patent number: 9355952
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Patent number: 9331017
    Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Tao Wu, Islam A. Salama
  • Patent number: 9266723
    Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Grant A. Crawford, Islam Salama
  • Patent number: 9211609
    Abstract: A method includes generating a laser beam and applying the beam to a substrate to form a via in the substrate. The laser beam has an intensity profile taken at a cross-section transverse to the direction of propagation of the beam. The intensity profile has a first substantially uniform level across an interior region of the cross-section and a second substantially uniform level across an exterior region of the cross-section. The second intensity level is greater than the first intensity level.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Islam A. Salama, Nathaniel R. Quick, Aravinda Kar
  • Patent number: 9202803
    Abstract: An apparatus including a package substrate including a plurality of layers of conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones of the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Chong Zhang, Stefanie M. Lotz, Qinglei Zhang, Sri Ranga Boyapati, Nikhil Sharma, Islam A. Salama
  • Publication number: 20150338718
    Abstract: An acousto-optic deflector with multiple acoustic transducers is described that is suitable for use in substrate processing. In one example a method includes transmitting an optic beam through an acousto-optic deflector, applying an acoustic signal with a phase delay across multiple transducers of the acousto-optic deflector to deflect the beam along a first axis by the acousto-optic deflector, and directing the deflected beam onto a workpiece.
    Type: Application
    Filed: April 17, 2015
    Publication date: November 26, 2015
    Inventors: Chong ZHANG, Aleksandar Aleksov, Islam A. Salama, Tiansi Wang, Aravinda Kar
  • Publication number: 20150318238
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Inventors: Mark S. HLAD, Islam A. SALAMA, Mihir K. ROY, Tao WU, Yueli LIU, Kyu Oh LEE
  • Publication number: 20150279817
    Abstract: An apparatus including a package substrate including a plurality of layers of conductive material, the package substrate including a cavity; and a device in the cavity, wherein an ultimate layer of the plurality of layers of conductive material defines contacts to contact points of the device. An apparatus including a package substrate comprising a plurality of conductive layers and a silicon bridge die disposed between ones of the plurality of conductive layers and an ultimate layer of the plurality of conductive layers defines contact points to contact points of the silicon bridge die; and a logic die coupled to the contact points of the ultimate layer of the plurality of layers of conductive layers.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Chong ZHANG, Stefanie M. LOTZ, Qinglei ZHANG, Sri Ranga BOYAPATI, Nikhil SHARMA, Islam A. SALAMA
  • Patent number: 9119313
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 25, 2015
    Assignee: INTEL CORPORATION
    Inventors: Chong Zhang, Stefanie M. Lotz, Islam A. Salama
  • Patent number: 9093313
    Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Mark S. Hlad, Islam A. Salama, Mihir K. Roy, Tao Wu, Yueli Liu, Kyu Oh Lee
  • Patent number: 9064798
    Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 23, 2015
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar, Islam A. Salama