Abstract: Implementations of the disclosure may include methods of electroplating features formed on a semiconductor device, such as the trenches and vias formed by single or dual Damascene processes using a cobalt plating bath. The cobalt electroplating bath may contain “additive packages” or “additive systems” that include a combination of additives in certain ratios that facilitate the metal filling of high aspect ratio sub-micrometer features. Implementations of the disclosure provide new cobalt plating bath methods and chemistries and that include alkyl modified imidazoles, imidazolines, and imidazolidines suppressor compounds.

Abstract: Methods and apparatus for forming an interconnect, including: depositing a first barrier layer upon a top surface of a via and a top surface of a trench; filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench; etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench; depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and filling the trench with a second metal different than the first metal.

Abstract: Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature disposed in a substrate includes (a) depositing a metal within the feature to a first predetermined thickness in a first process chamber; (b) depositing the metal within the feature to a second predetermined thickness in a second process chamber; (c) etching the metal deposited in (b) to remove an overhang of the metal at a top of the feature in a third process chamber different than the first and second process chambers; and (d) subsequent to (c), filling the feature with the metal in a fourth process chamber different than the first and third process chambers.

Abstract: Methods and apparatus for forming an interconnect, including: depositing a first barrier layer upon a top surface of a via and a top surface of a trench; filling the via with a first metal, wherein the first metal completely fills the via and forms a metal layer within the trench; etching the metal layer within the trench to expose dielectric sidewalls of the trench, a top surface of the via, and a dielectric bottom of the trench; depositing a second barrier layer upon the dielectric sidewalls, top surface of the via, and the dielectric bottom of the trench; and filling the trench with a second metal different than the first metal.

Abstract: Methods and apparatus for filling a feature disposed in a substrate, including: depositing a first metal within the feature to a first predetermined thickness in a first process chamber; etching the first metal to remove a first portion of the metal at a top of the feature in a second process chamber different than the first process chamber to form an exposed surface of the first metal, and selectively depositing a second metal atop the exposed surface of the first metal within the feature to a second predetermined thickness in a third process chamber; wherein etching the first metal and selectively depositing a second metal are performed without oxygen contacting the top surface.

Abstract: Methods and apparatus for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

Abstract: Methods for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

Abstract: Implementations of the disclosure may include methods of electroplating features formed on a semiconductor device, such as the trenches and vias formed by single or dual Damascene processes using a cobalt plating bath. The cobalt electroplating bath may contain “additive packages” or “additive systems” that include a combination of additives in certain ratios that facilitate the metal filling of high aspect ratio sub-micrometer features. Implementations of the disclosure provide new cobalt plating bath methods and chemistries and that include alkyl modified imidazoles, imidazolines, and imidazolidines suppressor compounds.

Abstract: Implementations of the disclosure may include methods of electroplating features formed on a semiconductor device, such as the trenches and vias formed by single or dual Damascene processes using a cobalt plating bath. The cobalt electroplating bath may contain “additive packages” or “additive systems” that include a combination of additives in certain ratios that facilitate the metal filling of high aspect ratio sub-micrometer features. Implementations of the disclosure provide new cobalt plating bath methods and chemistries and that include alkyl modified imidazoles, imidazolines, and imidazolidines suppressor compounds.

Abstract: Methods and apparatus for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

Abstract: Methods of etching tungsten are disclosed including: leveling a first top surface of a tungsten layer within a feature and atop a top surface of a substrate; and etching the tungsten layer with a peroxide such as hydrogen peroxide and one of a strong acid or a strong base to remove a first portion of the tungsten layer from atop the substrate to form a second top surface of a tungsten layer at a level below the top surface of the substrate. The methods are suitable for forming substantially level or flat top surfaces of a tungsten layer at a level below the top surface of the substrate or within one or more features such as vias or trenches.

Abstract: Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature disposed in a substrate includes (a) depositing a metal within the feature to a first predetermined thickness in a first process chamber; (b) depositing the metal within the feature to a second predetermined thickness in a second process chamber; (c) etching the metal deposited in (b) to remove an overhang of the metal at a top of the feature in a third process chamber different than the first and second process chambers; and (d) subsequent to (c), filling the feature with the metal in a fourth process chamber different than the first and third process chambers.

Abstract: Implementations of the disclosure may include methods of electroplating features formed on a semiconductor device, such as the trenches and vias formed by single or dual Damascene processes using a cobalt plating bath. The cobalt electroplating bath may contain “additive packages” or “additive systems” that include a combination of additives in certain ratios that facilitate the metal filling of high aspect ratio sub-micrometer features. Implementations of the disclosure provide new cobalt plating bath methods and chemistries and that include alkyl modified imidazoles, imidazolines, and imidazolidines suppressor compounds.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.

Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.

Abstract: A method and apparatus for a copper electroplating procedure, wherein a first additive is preferentially adsorbed onto the field region of a substrate and a second additive is preferentially adsorbed onto the surfaces of at least one recessed region of the substrate, is provided. The first additive is more resistive to the electrodeposition relative to the second additive such that the recessed regions are filled at a faster rate than a layer is deposited on the field region.