Patents by Inventor Ivan Leonidovich Mazurenko

Ivan Leonidovich Mazurenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9542748
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Patent number: 9384556
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Patent number: 9362977
    Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 9336431
    Abstract: A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: May 10, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin
  • Patent number: 9294128
    Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Denis Vladimirovich Zaytsev, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Pavel Aleksandrovich Aliseitchik, Dmitry Nicolaevich Babin
  • Patent number: 9184787
    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Meng-Lin Yu, Jian-Guo Chen, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko
  • Publication number: 20150310264
    Abstract: In one embodiment, an image processor comprises image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system implemented by the image processor comprises a dynamic gesture recognition module. The dynamic gesture recognition module is configured to establish a dynamic gesture recognition interval comprising a plurality of image frames, to extract one or more first features from the dynamic gesture recognition interval, to adjust the dynamic gesture recognition interval, to extract one or more second features from the adjusted dynamic gesture recognition interval, and to recognize a dynamic gesture based at least in part on at least a subset of the extracted first and second features.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 29, 2015
    Inventors: Pavel Aleksandrovich Aliseitchik, Ivan Leonidovich Mazurenko, Aleksey Alexandrovich Letunovskiy, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Publication number: 20150302593
    Abstract: Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 22, 2015
    Applicant: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Pavel Aleksandrovich Aliseitchik, Alexander Borisovich Kholodenko, Denis Vasilyevich Parfenov, Denis Vladimirovich Parkhomenko
  • Publication number: 20150278589
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system implemented by the image processor comprises a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to determine a contour of the hand region of interest, to triangulate the determined contour, to flatten the triangulated contour, to compute one or more features of the flattened contour, and to recognize a static pose of the hand region of interest based at least in part on the one or more computed features.
    Type: Application
    Filed: March 25, 2015
    Publication date: October 1, 2015
    Inventors: Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko
  • Publication number: 20150269740
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Publication number: 20150253864
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system utilizing the image processing circuitry and the memory. The gesture recognition system comprises a finger detection and tracking module configured to identify a hand region of interest in a given image, to extract a contour of the hand region of interest, to detect fingertip positions using the extracted contour, and to track movement of the fingertip positions over multiple images including the given image.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 10, 2015
    Inventors: Denis Vladimirovich Parkhomenko, Ivan Leonidovich Mazurenko, Dmitry Nicolaevich Babin, Denis Vladimirovich Zaytsev, Aleksey Alexandrovich Letunovskiy
  • Publication number: 20150253863
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to obtain a vocabulary of hand poses, to estimate a plurality of hand features based on the hand region of interest, the plurality of hand features comprising a first set of features estimated from the hand region of interest and a second set of features comprising at least one feature estimated using a transform on a contour of the hand region of interest, and to recognize a static pose of the hand region of interest based on the first set of features and the second set of features, wherein respective numbers of features in the first set of features and the second set of features are based at least in part on a size of the vocabulary of hand poses.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 10, 2015
    Inventors: Dmitry Nicolaevich Babin, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Denis Vladimirovich Zaytsev
  • Patent number: 9037944
    Abstract: A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 19, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Alexander Alexandrovich Petyushko, Anatoli Aleksandrovich Bolotov, Yang Han, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov
  • Patent number: 8977925
    Abstract: A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 10, 2015
    Assignee: LSI Corporation
    Inventors: Denis Vladimirovich Zaytsev, Denis Vasilievich Parfenov, Yang Han, Ivan Leonidovich Mazurenko, Dmitry Nicolaevich Babin
  • Patent number: 8832532
    Abstract: An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Anatoli A. Bolotov, Aleksey Alexandrovich Letunovskiy, Ivan Leonidovich Mazurenko, Lav D. Ivanovic, Fan Zhang
  • Patent number: 8824667
    Abstract: In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the acoustic echo originated. The AEC module determines whether or not samples of the incoming signal contain acoustic echo based on the aligned outgoing signal, and the determinations are applied to a hangover counter. The AEC module then suppresses acoustic echo in the incoming signal and adds comfort noise to the incoming signal. The amount of echo suppression performed is gradually increased or decreased based on comparisons of the counter to a hangover threshold.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 2, 2014
    Assignee: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Dmitry Nikolaevich Babin, Denis Vassilevich Parfenov, Alexander Alexandrovich Petyushko, Alexander Markovic
  • Publication number: 20140245086
    Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.
    Type: Application
    Filed: September 16, 2013
    Publication date: August 28, 2014
    Applicant: LSI Corporation
    Inventors: Denis Vladimirovich Zaytsev, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Pavel Aleksandrovich Aliseitchik, Dmitry Nicolaevich Babin
  • Publication number: 20140226854
    Abstract: A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
    Type: Application
    Filed: August 22, 2013
    Publication date: August 14, 2014
    Applicant: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko, Dmitry Nicolaevich Babin
  • Publication number: 20140226895
    Abstract: A method and system for registration of three-dimensional (3D) image frames is disclosed. The method includes receiving two point clouds representing two 3D image frames obtained at two time instances; locating the origins for the two point clouds; constructing two 2D grids for representing the two point clouds, wherein each 2D grid is constructed based on spherical representation of its corresponding point cloud and origin; identifying two sets of feature points based on the two 2D grids constructed; establishing a correspondence between the first set of feature points and the second set of feature points based on a neighborhood radius threshold; and determining an orthogonal transformation between the first 3D image frame and the second 3D image frame based on the correspondence between the first set of feature points and the second set of feature points.
    Type: Application
    Filed: August 21, 2013
    Publication date: August 14, 2014
    Applicant: LSI Corporation
    Inventors: Dmitry Nicolaevich Babin, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko, Alexander Borisovich Kholodenko, Denis Vladimirovich Parkhomenko
  • Patent number: 8780983
    Abstract: A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 15, 2014
    Assignee: LSI Corporation
    Inventors: Ivan Leonidovich Mazurenko, Aleksey Alexandrovich Letunovskiy, Alexander Markovic, Denis Vassilevich Parfenov, Alexander Alexandrovich Petyushko