Abstract: An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal.

Abstract: A technique for fabricating a hybrid optical source is described. During this fabrication technique, a III-V compound-semiconductor active gain medium is integrated with a silicon-on-insulator (SOI) chip (or wafer) using edge coupling to form a co-planar hybrid optical source. Using a backside etch-assisted cleaving technique, and a temporary transparent substrate with alignment markers, a III-V compound-semiconductor chip with proper edge polish and coating can be integrated with a processed SOI chip (or wafer) with accurate alignment. This fabrication technique may significantly reduce the alignment complexity when fabricating the hybrid optical source, and may enable wafer-scale integration.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Abstract: A multi-level interposer plate and a multi-chip module (MCM) that includes the multi-level interposer plate are described. First surfaces and second surfaces in different regions of the multi-level interposer plate have associated, different thicknesses. Moreover, first micro-spring connectors and second micro-spring connectors are respectively disposed on the first surfaces and the second surfaces. In the MCM, a given one of the first surfaces of the multi-level interposer plate faces a bridge chip in a first layer in an array of chips in the MCM so that first connectors, disposed on the bridge chip, mechanically and electrically couple to the first micro-spring connectors. Similarly, a given one of the second surfaces of the multi-level interposer plate faces an island chip in a second layer in the array of chips so that second connectors, disposed on the island chip, mechanically and electrically couple to the second micro-spring connectors.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal.

Abstract: A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon <110> facet at an angle of 45° when etched through the <100> surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

Abstract: An integrated circuit is described. This integrated circuit includes an optical waveguide defined in a semiconductor layer, and an optical detector disposed on top of the optical waveguide. Moreover, the optical waveguide has an end with a reflecting facet. For example, the reflective facet may be defined using an anisotropic etch of the semiconductor layer. This reflecting facet reflects light propagating in a plane of the optical waveguide out of the plane into the optical detector, thereby providing a photodetector with high optical responsivity, including an extremely low dark current (and, thus, high photosensitivity) and an extremely small capacitance (and, thus, high electrical bandwidth).

Abstract: An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal.

Abstract: An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal.

Abstract: A hybrid optical source that provides an optical signal having a wavelength is described. This hybrid optical source includes an edge-coupled optical amplifier (such as a III-V semiconductor optical amplifier) aligned to a semiconductor reflector (such as an etched silicon mirror). The semiconductor reflector efficiently couples (i.e., with low optical loss) light out of the optical amplifier in a direction approximately perpendicular to a plane of the optical amplifier. A corresponding optical coupler (such as a diffraction grating or a mirror) fabricated on a silicon-on-insulator chip efficiently couples the light into a sub-micron silicon-on-insulator optical waveguide. The silicon-on-insulator optical waveguide couples the light to additional photonic elements (including a reflector) to complete the hybrid optical source.

Abstract: A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip.

Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

Abstract: An optical device with high thermal tuning efficiency is described. This optical device may be implemented using a tri-layer structure (silicon-on-insulator technology), including: a substrate, a buried-oxide layer and a semiconductor layer. In particular, a thermally tunable optical waveguide may be defined in the semiconductor layer. Furthermore, a portion of the substrate under the buried-oxide layer and substantially beneath a location of the thermally tunable optical waveguide is fabricated so that a portion of the buried-oxide layer is exposed. In this way, the thermal impedance between the thermally tunable optical waveguide and an external environment is increased, and power consumption associated with thermal tuning of the optical waveguide is reduced.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Abstract: In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: An optical device implemented on a substrate (such as silicon) is described. This optical device includes a wavelength-sensitive optical component with a high thermal resistance to a surrounding external environment and a low thermal resistance to a localized thermal-tuning mechanism (such as a heater), which modifies a temperature of the wavelength-sensitive optical component, thereby specifying an operating wavelength of the wavelength-sensitive optical component. In particular, the thermal resistance associated with a thermal dissipation path from the thermal-tuning mechanism to the external environment via the substrate is increased by removing a portion of the substrate to create a gap that is proximate to the thermal-tuning mechanism and the wavelength-sensitive optical component. Furthermore, the optical device includes a binder material mechanically coupled to the substrate and proximate to the gap, thereby maintaining a mechanical strength of the optical device.