Patents by Inventor Iwao Higashikawa

Iwao Higashikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6165652
    Abstract: A method of forming a photomask of a semiconductor device comprising the steps of forming a photosensitive film on a substrate and exposing the photosensitive film on the substrate by radiating with a radiation beam a plurality of butting unit regions defining butting portions between the butting unit regions and controlling said radiating of the butting unit region so that the butting portions of the butting unit regions are formed only in portions corresponding to isolation regions or alternatively, they are not formed in portions corresponding to contact areas.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 6040114
    Abstract: A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern f
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: March 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 5969428
    Abstract: An alignment mark formed on a surface of substrate for aligning with a mask through an irradiation of alignment light, which comprises a step formed with a concave portion and a convex portion and a metallic film deposited along the concave portion and the convex portion. A light absorption layer is formed over at least one of the concave portion and the convex portion reflecting the step, the light absorption layer lying over the concave portion having a different thickness from that of the light absorption layer lying over the convex portion when the light absorption layer is formed over both the concave portion and the convex portion, the light absorption layer comprising a material capable of absorbing at least a portion of wavelength region of the alignment light. The light absorption layer is desirably formed in a larger thickness on the convex portion of the step as compared with that on the concave portion.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nomura, Iwao Higashikawa, Akitoshi Kumagae
  • Patent number: 5907393
    Abstract: This invention provides an exposure mask including a translucent film formed on a light-transmitting substrate and having a mask pattern, and a stabilized region formed in the boundary between the light-transmitting substrate and the translucent film or on at least the surface of the translucent film to prevent variations in physical properties of the translucent film.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: May 25, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Iwao Higashikawa, Masamitsu Itoh, Takashi Kamo, Hiroaki Hazama, Takayuki Iwamatsu
  • Patent number: 5851842
    Abstract: The measurement system comprises a holder for holding a dielectric film formed on at least a semiconductive substrate and sandwiched between the substrate and a conductive film, voltage application terminals for applying voltage between the substrate and the conductive film, variable voltage source for supplying the voltage to the voltage application terminals, a light source for irradiating the dielectric film with light including wavelength of an infrared region and transmitting the light through the dielectric film, light absorbance detector receiving the light transmitted through the dielectric film, for detecting absorbance of an absorbed light component in an absorption wavelength region intrinsic to the dielectric film, and a potential difference measurement unit for measuring a potential difference between the substrate and the conductive film of the dielectric film on the basis of change in absorbance of the light component when the voltage is changed by the variable voltage source.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: December 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Katsumata, Nobuo Hayasaka, Naoki Yasuda, Hideshi Miyajima, Iwao Higashikawa, Masaki Hotta
  • Patent number: 5847468
    Abstract: An alignment mark formed on a surface of substrate for aligning with a mask through an irradiation of alignment light, which comprises a step formed with a concave portion and a convex portion and a metallic film deposited along the concave portion and the convex portion. A light absorption layer is formed over at least one of the concave portion and the convex portion reflecting the step, the light absorption layer lying over the concave portion having a different thickness from that of the light absorption layer lying over the convex portion when the light absorption layer is formed over both the concave portion and the convex portion, the light absorption layer comprising a material capable of absorbing at least a portion of wavelength region of the alignment light. The light absorption layer is desirably formed in a larger thickness on the convex portion of the step as compared with that on the concave portion.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: December 8, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nomura, Iwao Higashikawa, Akitoshi Kumagae
  • Patent number: 5767521
    Abstract: An electron-beam lithography system employing an "electron holography" technique is disclosed. The system at least comprises: a shaping aperture for shaping an electron beam emitted from an electron-beam source so as to have a specific beam shape; at least two single crystal thin films for diffracting the electron beam passed through this shaping aperture; focusing means for respectively focusing the incident electron beam passed through these single crystal thin films and the diffracted electron beams diffracted by these single crystal thin films; and a select aperture for selecting only the desired diffracted electron beams. The transmitted incident electron beam interferes with the diffracted electron beams, whereby a stripe pattern having a desired nanometer-order pitch is formed on a resist surface coated onto a semiconductor substrate or a mask blank.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: June 16, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiro Takeno, Shigeru Kanbayashi, Mitsuo Koike, Seizo Doi, Iwao Higashikawa
  • Patent number: 5728494
    Abstract: This invention provides an exposure mask including a translucent film formed on a light-transmitting substrate and having a mask pattern, and a stabilized region formed in the boundary between the light-transmitting substrate and the translucent film or on at least the surface of the translucent film to prevent variations in physical properties of the translucent film.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: March 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Iwao Higashikawa, Masamitsu Itoh, Takashi Kamo, Hiroaki Hazama, Takayuki Iwamatsu
  • Patent number: 5629115
    Abstract: This invention provides an exposure mask including a translucent film formed on a light-transmitting substrate and having a mask pattern, and a stabilized region formed in the boundary between the light-transmitting substrate and the translucent film or on at least the surface of the translucent film to prevent variations in physical properties of the translucent film.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Iwao Higashikawa, Masamitsu Itoh, Takashi Kamo, Hiroaki Hazama, Takayuki Iwamatsu
  • Patent number: 5374502
    Abstract: In accordance with a proposed resist pattern forming method, contact angles between the surface of a resist and a rinse is adjusted within a predetermined range, a volatil surfactant which does not remain by drying is mixed in the rinse so as to reduce a surface tension, the rinse is dried under a critical condition of the rinse in order not to cause the surface tension to exert. The occurrence of an attractive force between the resist patterns may be thereby weakened or nullified, so that falling of the patterns can be effectively prevented which very often happened at forming fine resist patterns or resist patterns of high aspect. On the other hand, depending upon structure of said resist pattern, it is possible to effectively prevent outermost main patterns of gathering resist patterns from falling down. By providing such effects, yieldings of products are increased. Further, the present invention may be also applied to a lithography illumination sources of which are light, electron, X-ray, ion beam, etc.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: December 20, 1994
    Assignee: SORTEC Corporation
    Inventors: Toshihiko Tanaka, Mitsuaki Morigami, Iwao Higashikawa, Takeo Watanabe
  • Patent number: 5326672
    Abstract: In accordance with a proposed resist pattern forming method, contact angles between the surface of a resist and a rinse is adjusted within a predetermined range, a volatil surfactant which does not remain by drying is mixed in the rinse so as to reduce a surface tension, the rinse is dried under a critical condition of the rinse in order not to cause the surface tension to exert. The occurrence of an attractive force between the resist patterns may be thereby weakened or nullified, so that falling of the patterns can be effectively prevented which very often happened at forming fine resist patterns or resist patterns of high aspect. On the other hand, depending upon structure of said resist pattern, it is possible to effectively prevent outermost main patterns of gathering resist patterns from falling down. By providing such effects, yielding of products are increased. Further, the present invention may be also applied to a lithography illumination sources of which are light, electron, X-ray, ion beam, etc.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: July 5, 1994
    Assignee: SORTEC Corporation
    Inventors: Toshihiko Tanaka, Mitsuaki Morigami, Iwao Higashikawa, Takeo Watanabe
  • Patent number: 5262282
    Abstract: A pattern forming method of a resist to be used in the manufacturing process of a semiconductor device. The desired area of a resist film is made hydrophilic by an exposure and a mask material is precipitated and deposited on the area of resist film made hydrophilic in the solution. The patterning of resist film is thus carried out, and a pattern of high reliability is formed. After exposure, by silylizing or baking the resist film, a pattern of higher reliability is formed. Furthermore, after patterning of the resist film, the precipitation and deposition of the mask material are carried out again, and a reversed pattern of high reliability is formed by eliminating the resist film made with patterning by the lift-off process.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: November 16, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Iwao Higashikawa
  • Patent number: 4510173
    Abstract: A flat film can be formed on a functional structure having uneven surface formed on a semiconductor substrate firstly by applying a film-forming organic material capable of being cured by energy beams and exhibiting fluidity by heat on the uneven surface of the functional structure. Then, the organic material is fluidized by applying heat to the applied organic material, thereby substantially flattening the surface of the organic material. Energy beams are irradiated to the flattened organic material to cure the flattened organic material, thereby converting the flattened organic material into a cured film which is not deformed by heat and energy beams.
    Type: Grant
    Filed: April 19, 1984
    Date of Patent: April 9, 1985
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Higashikawa, Tsunetoshi Arikado
  • Patent number: 4473437
    Abstract: A dry etching method for organic material layers is disclosed which utilizes a parallel plate electrode type plasma etching apparatus. An etching gas containing nitrogen as its primary constituent is introduced into the apparatus, and then the organic material layers are anisotropically etched by applying a high frequency electric power to the electrodes to produce a plasma.
    Type: Grant
    Filed: November 16, 1983
    Date of Patent: September 25, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Iwao Higashikawa, Tsunetoshi Arikado
  • Patent number: 4264715
    Abstract: A method of preparing a fine and highly precise resist pattern comprising a step of forming a positive resist layer consisting of poly-(methacrylic anhydride) on a substrate, a step of irradiating the resist layer thus formed with a predetermined pattern of ionizing radiation and a step of developing the irradiated resist pattern with a developer comprising a solvent mixture composed of a polar organic solvent (A) capable of dissolving poly-(methyacrylic anhydride) and a non-solvent (B) incapable of dissolving poly-(methacrylic anhydride).
    Type: Grant
    Filed: November 14, 1979
    Date of Patent: April 28, 1981
    Assignee: VLSI Technology Research Association
    Inventors: Akira Miura, Shozo Hideyama, Iwao Higashikawa