Patents by Inventor Iyun Leu

Iyun Leu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11774373
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. This method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 3, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Patent number: 11774372
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. This method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 3, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Patent number: 11761904
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. This method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 19, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Patent number: 11719649
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. The method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 8, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Patent number: 11719648
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. The method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 8, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Patent number: 11719650
    Abstract: A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab are provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. The method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: August 8, 2023
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventor: Iyun Leu
  • Publication number: 20210231582
    Abstract: The present invention relates to a smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Iyun LEU, Ray Jenn TSAY
  • Publication number: 20210231581
    Abstract: The present invention relates to a smart defect calibration, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: IYUN LEU, RAY JENN TSAY
  • Publication number: 20210231583
    Abstract: The present invention relates to a smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: IYUN LEU, RAY JENN TSAY
  • Publication number: 20210231579
    Abstract: The present invention relates to a smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: IYUN LEU, RAY JENN TSAY
  • Publication number: 20210231584
    Abstract: The present invention relates to a smart defect calibration, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: IYUN LEU, RAY JENN TSAY
  • Publication number: 20210231580
    Abstract: The present invention relates to a smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: IYUN LEU, RAY JENN TSAY
  • Patent number: 11016035
    Abstract: A smart defect calibration, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes: receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system, selecting defect samples based on the defect classification data, selecting alarm defect and filtering false defect with pattern match with defect pattern library and frequent failure defect library, performing coordinate conversion and pattern match between defect image contour, defect image pattern, and design layout for coordinate correction, creating a CAA accuracy correction system and defect size calibration system by analyzing original defect size data and defect contour size from image analysis, evaluating the defect size using measurement uncertainty analysis with statistical analysis methods to reach the purposes of increasing CAA accuracy and Killer Defect identification rate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 25, 2021
    Assignee: Elite Semiconductor Inc.
    Inventor: Iyun Leu
  • Patent number: 10726192
    Abstract: The present invention relates to “an Innovative Semiconductor Fab's Defect Operating System” thereof for design house and manufacturing Fab is provided. The Innovative Semiconductor Fab's Defect Operating System comprises: receiving pluralities of defect data, IC design layout data; analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) method via a Defect Operating System located inside the Fab site; identify a killer or non-killer defect based on the open or short failure probability; sending the killer defect data to the design house via internet, FTP, etc. The design house receives the wafer testing yield data; pick the bad die information and the killer defect information for failure analysis; correlate the corresponding defect data with the wafer test data; sending the failure killer defect data to the Fab via internet, FTP, etc.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 28, 2020
    Assignee: ELITE SEMICONDUCTOR INC.
    Inventors: Iyun Leu, Ray Jenn Tsay
  • Patent number: 10719655
    Abstract: The present disclosure provides a system and a method for quickly diagnosing, classifying, and sampling in-line defects based on a CAA pre-diagnosis database. The method includes the steps of obtaining a design layout of an object and a defect data of an important process stage of the object, obtaining a pre-diagnosis data group related to the design layout from a CAA pre-diagnosing database, and judging a killer defect index and a failure risk level of the defect data according to the pre-diagnosis data group.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 21, 2020
    Assignee: ELITE SEMICONDUCTOR, INC.
    Inventor: Iyun Leu
  • Publication number: 20200026819
    Abstract: The present invention relates to “an Innovative Semiconductor Fab's Defect Operating System” thereof for design house and manufacturing Fab is provided. The Innovative Semiconductor Fab's Defect Operating System comprises: receiving pluralities of defect data, IC design layout data; analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) method via a Defect Operating System located inside the Fab site; identify a killer or non-killer defect based on the open or short failure probability; sending the killer defect data to the design house via internet, FTP, etc. The design house receives the wafer testing yield data; pick the bad die information and the killer defect information for failure analysis; correlate the corresponding defect data with the wafer test data; sending the failure killer defect data to the Fab via internet, FTP, etc.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 23, 2020
    Inventors: Iyun LEU, Ray Jenn TSAY
  • Patent number: 10409924
    Abstract: The instant disclosure provides an intelligent CAA (Critical Area Analysis) failure pre-diagnosis system and method for a design layout. The intelligent CAA failure pre-diagnosis method includes the steps of obtaining a design layout of an object and defining at least one layout region having a layout pattern thereon, obtaining a plurality of defects, comparing the defects one-by-one to a predetermined portion of the layout pattern in the order of their sizes, and calculating a CAA failure risk level of the layout region according to the comparison result.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 10, 2019
    Assignee: ELITE SEMICONDUCTOR, INC.
    Inventor: Iyun Leu
  • Patent number: 10312164
    Abstract: Disclosure herein is related to a method and a system for intelligent weak pattern diagnosis for semiconductor product, and a related non-transitory computer-readable storage medium. In the method, a weak pattern layout is firstly retrieved from a defect pattern library and a frequent failure defect pattern library; defect data is retrieved from fab defect inspection tool; a design layout is then received and weak defect pattern screen is performed to extract known and unknown weak defect patterns. In addition to updating the weak pattern library, the weak pattern contour can be made upon SEM image data, and then the true systematic weak pattern can be justified.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: June 4, 2019
    Assignee: ELITE SEMICONDUCTOR, INC.
    Inventor: Iyun Leu
  • Publication number: 20190086340
    Abstract: The present invention relates to a Smart Defect Calibration, Diagnosis, Sampling System and The Method Thereof for manufacturing fab is provided.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 21, 2019
    Inventor: IYUN LEU
  • Patent number: 10228421
    Abstract: Disclosure is related to a method and a system for intelligent defect classification and sampling, and a computer-readable storage device. The computer-implemented method acquires in-line defect inspection file, and retrieves the defect patterns over a device under test, e.g. a wafer from a fab. The system incorporates a defect pattern recognition engine to recognize the defect signature patterns from the defect patterns. A sampling scheme is performed to acquire weak defect patterns. A critical area analysis based on failure probability of weak patterns is incorporated to performing the sampling. The defect layout pattern groups probably causing the open or short failure can be obtained. The defect signature patterns through sampling are then displayed using a browsing system. Through a user interface, the user can perform functions, such as filtering, selection and merging, onto the defect patterns.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 12, 2019
    Assignee: Elite Semiconductor, Inc.
    Inventor: Iyun Leu