Patents by Inventor Izak Bencuya
Izak Bencuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7148111Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: GrantFiled: August 27, 2004Date of Patent: December 12, 2006Assignee: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean E. Probst
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Publication number: 20050153497Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.Type: ApplicationFiled: November 24, 2004Publication date: July 14, 2005Inventors: Izak Bencuya, Brian Mo, Ashok Challa
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Publication number: 20050079676Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: ApplicationFiled: August 27, 2004Publication date: April 14, 2005Applicant: Fairchild Semiconductor CorporationInventors: Brian Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Probst
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Patent number: 6828195Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: GrantFiled: January 17, 2003Date of Patent: December 7, 2004Assignee: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Publication number: 20040145015Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: ApplicationFiled: July 30, 2003Publication date: July 29, 2004Applicant: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Publication number: 20040142523Abstract: A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.Type: ApplicationFiled: January 8, 2004Publication date: July 22, 2004Inventors: Izak Bencuya, Brian Sze-Ki Mo, Ashok Challa
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Patent number: 6710406Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: GrantFiled: May 24, 2002Date of Patent: March 23, 2004Assignee: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Patent number: 6696726Abstract: A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.Type: GrantFiled: August 16, 2000Date of Patent: February 24, 2004Assignee: Fairchild Semiconductor CorporationInventors: Izak Bencuya, Brian Sze-Ki Mo, Ashok Challa
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Publication number: 20030127688Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: ApplicationFiled: January 17, 2003Publication date: July 10, 2003Applicant: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Publication number: 20020140027Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: ApplicationFiled: May 24, 2002Publication date: October 3, 2002Inventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Patent number: 6429481Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: GrantFiled: November 14, 1997Date of Patent: August 6, 2002Assignee: Fairchild Semiconductor CorporationInventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
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Patent number: 6423623Abstract: A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.Type: GrantFiled: August 27, 1998Date of Patent: July 23, 2002Assignee: Fairchild Semiconductor CorporationInventors: Izak Bencuya, Maria Christina B. Estacio, Steven P. Sapp, Consuelo N. Tangpuz, Gilmore S. Baje, Rey D. Maligro
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Patent number: 5879994Abstract: An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed.Type: GrantFiled: April 15, 1997Date of Patent: March 9, 1999Assignee: National Semiconductor CorporationInventors: Sze-Hon Kwan, Izak Bencuya, Steven P. Sapp
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Patent number: 5767550Abstract: In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is also a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The presence of the field plate creates a special protection device similar to a zener diode, but which exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the length of the field plate.Type: GrantFiled: October 16, 1996Date of Patent: June 16, 1998Assignee: National Semiconductor CorporationInventors: Daniel Calafut, Izak Bencuya, Steven Sapp
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Patent number: 5665619Abstract: A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.Type: GrantFiled: May 13, 1996Date of Patent: September 9, 1997Assignee: National Semiconductor CorporationInventors: Sze-Hon Kwan, Izak Bencuya
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Patent number: 5605852Abstract: For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts.Type: GrantFiled: May 18, 1995Date of Patent: February 25, 1997Assignee: Siliconix IncorporatedInventor: Izak Bencuya
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Patent number: 5602046Abstract: In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The field plate creates a protection device similar to a zener diode, but exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the field plate length.Type: GrantFiled: April 12, 1996Date of Patent: February 11, 1997Assignee: National Semiconductor CorporationInventors: Daniel Calafut, Izak Bencuya, Steven Sapp
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Patent number: 5567634Abstract: A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.Type: GrantFiled: May 1, 1995Date of Patent: October 22, 1996Assignee: National Semiconductor CorporationInventors: Francois Hebert, Sze-Hon Kwan, Izak Bencuya
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Patent number: 5430324Abstract: For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts.Type: GrantFiled: July 23, 1992Date of Patent: July 4, 1995Assignee: Siliconix, IncorporatedInventor: Izak Bencuya
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Patent number: 5136349Abstract: A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.Type: GrantFiled: October 12, 1990Date of Patent: August 4, 1992Assignee: Siliconix IncorporatedInventors: Hamza Yilmaz, Izak Bencuya