Abstract: An insulated gate transistor (70) modified to increase its latching current density. On one side of gate (22), a high conductivity collector well (76) is provided to divert current which would otherwise flow through collector well (24) in a critical path (50) along source-collector junction (27), tending to forward bias the junction and cause the transistor to latch.

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface.

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges.

Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions.

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges.

Abstract: Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. The depth of the grooves is increased by etching to remove most of the P-type zone underlying each groove while leaving laterally extending P-type portions. Oxygen is implanted to convert the remainder of the P-type zones underlying the end walls of the grooves to silicon dioxide. Metal layers are deposited in the bottoms of the grooves making contact with the P-type portions.

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface.

Abstract: Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. Metal contacts are applied to the P-type zones at the end walls of the grooves. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface.