Patents by Inventor Izumi Tanaka

Izumi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11219128
    Abstract: A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 4, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Izumi Tanaka
  • Publication number: 20210045242
    Abstract: A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 11, 2021
    Inventor: Izumi TANAKA
  • Patent number: 10887985
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 5, 2021
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Publication number: 20190230791
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Natsuko KITAJO, Yuji YUKIIRI, Izumi TANAKA
  • Patent number: 10306759
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 28, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Publication number: 20180184521
    Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 28, 2018
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Patent number: 9711461
    Abstract: A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 18, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
  • Publication number: 20170141044
    Abstract: A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 18, 2017
    Inventors: NATSUKO KITAJO, YUJI YUKIIRI, IZUMI TANAKA
  • Patent number: 8697230
    Abstract: To provide a graphene sheet that has a large area, is homogeneous, and has a small amount of domain boundaries, a novel method for producing a graphene sheet suitable for industrial applications, such as application to electronics, that is capable of producing a graphene sheet that has well aligned crystal orientation at a low cost, and a graphene sheet. In the method for producing a graphene sheet of the present invention, a substrate containing a single crystal substrate having formed on the surface thereof an epitaxial metal film is used, and a graphene sheet is grown by making a carbon material into contact with the surface of the epitaxial metal film. In the graphene sheet of the present invention, the graphene sheet is constituted by a number of graphene domains, the domains each have an area of from 0.000001 ?m2 to 100,000 mm2, and the orientations of 6-membered rings in the domains are averagely aligned in a single direction over the graphene sheet.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 15, 2014
    Assignee: Kyushu University
    Inventors: Hiroki Ago, Yoshito Ito, Izumi Tanaka, Seigi Mizuno, Masaharu Tsuji
  • Patent number: 8561293
    Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 22, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Yukiiri, Izumi Tanaka
  • Publication number: 20120204424
    Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 16, 2012
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji YUKIIRI, Izumi Tanaka
  • Publication number: 20120196074
    Abstract: To provide a graphene sheet that has a large area, is homogeneous, and has a small amount of domain boundaries, a novel method for producing a graphene sheet suitable for industrial applications, such as application to electronics, that is capable of producing a graphene sheet that has well aligned crystal orientation at a low cost, and a graphene sheet. In the method for producing a graphene sheet of the present invention, a substrate containing a single crystal substrate having formed on the surface thereof an epitaxial metal film is used, and a graphene sheet is grown by making a carbon material into contact with the surface of the epitaxial metal film. In the graphene sheet of the present invention, the graphene sheet is constituted by a number of graphene domains, the domains each have an area of from 0.000001 ?m2 to 100,000 mm2, and the orientations of 6-membered rings in the domains are averagely aligned in a single direction over the graphene sheet.
    Type: Application
    Filed: August 31, 2010
    Publication date: August 2, 2012
    Applicant: KYUSHU UNIVERSITY
    Inventors: Hiroki Ago, Yoshito Ito, Izumi Tanaka, Seigi Mizuno, Masaharu Tsuji
  • Publication number: 20120144666
    Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.
    Type: Application
    Filed: February 17, 2012
    Publication date: June 14, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuji YUKIIRI, Izumi Tanaka
  • Patent number: 8196296
    Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: June 12, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Yukiiri, Izumi Tanaka
  • Patent number: 8049463
    Abstract: A stacked battery module or a battery pack is formed by laying a plurality of unit batteries of non-aqueous electrolyte batteries in layers with the surfaces thereof having a large area disposed vis-à-vis and electrically connecting them in series and a temperature fuse is arranged in the central part of the stacked battery module with one of its terminals connected to either the positive electrode terminal or the negative electrode terminal of the stacked battery module while the other terminal connected to a charging terminal for supplying a charging current in a charging operation. One of the terminals of the stacked battery module is connected to a discharging terminal for taking out a discharging current in a discharging operation and the other terminal of the stacked battery module is a common terminal for charging and discharging operations.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: November 1, 2011
    Assignee: NEC Energy Devices, Ltd.
    Inventors: Tomokazu Kumeuchi, Koichi Zama, Isao Tochihara, Izumi Tanaka
  • Publication number: 20090100673
    Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 23, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuji YUKIIRI, Izumi TANAKA
  • Patent number: 7380774
    Abstract: A humidifier is superior in terms of hygiene, simple in terms of maintenance, humidity is easily adjusted, and energy consumption is low. The humidifier uses, as a moisture permeable membrane, a moisture-permeable polyurethane obtained by using, as raw materials, at least an isocyanate component, a diol as a chain extender, and polyethylene glycol as a polyol component, and reacting these raw materials.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: June 3, 2008
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Yasuhiro Akita, Shunichi Hayashi, Hiroshi Mizutani, Norio Miwa, Akio Yagi, Takashi Nitta, Tadao Takahashi, Izumi Tanaka
  • Publication number: 20070120526
    Abstract: A stacked battery module or a battery pack is formed by laying a plurality of unit batteries of non-aqueous electrolyte batteries in layers with the surfaces thereof having a large area disposed vis-à-vis and electrically connecting them in series and a temperature fuse is arranged in the central part of the stacked battery module with one of its terminals connected to either the positive electrode terminal or the negative electrode terminal of the stacked battery module while the other terminal connected to a charging terminal for supplying a charging current in a charging operation. One of the terminals of the stacked battery module is connected to a discharging terminal for taking out a discharging current in a discharging operation and the other terminal of the stacked battery module is a common terminal for charging and discharging operations.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 31, 2007
    Applicant: NEC TOKIN CORPORATION
    Inventors: Tomokazu Kumeuchi, Koichi Zama, Isao Tochihara, Izumi Tanaka
  • Publication number: 20050252982
    Abstract: There is provided a humidifier superior in terms of hygiene, simple in terms of maintenance, wherein humidity is easily adjusted, and energy consumption is low. The humidifier uses as a moisture permeable membrane, a moisture-permeable polyurethane obtained by using as raw materials, at least an isocyanate component, a diol as a chain extender, and polyethylene glycol as a polyol component, and reacting these raw materials.
    Type: Application
    Filed: May 17, 2004
    Publication date: November 17, 2005
    Inventors: Yasuhiro Akita, Shunichi Hayashi, Hiroshi Mizutani, Norio Miwa, Akio Yagi, Takashi Nitta, Tadao Takahashi, Izumi Tanaka
  • Patent number: 4500899
    Abstract: The present invention is an improvement of a semiconductor memory device, preferably a PROM or a mask ROM, wherein: MOS transistors are formed in a semiconductor substrate, are arranged in rows, and are isolated from each other by a plurality of field insulation films arranged in an island pattern; the MOS transistors aligned in one of the rows have one common gate which extends over one row of field insulation films; the MOS transistors aligned in one of the rows have a common first region for forming a drain or a source parallel to the common gates; and a second region for forming another drain or source is surrounded by a pair of common gates and a pair of field insulation films so that a plurality of second regions are isolated from each other.
    Type: Grant
    Filed: December 23, 1981
    Date of Patent: February 19, 1985
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka