Patents by Inventor Izumi Tanaka

Izumi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4405995
    Abstract: An improved semiconductor memory device is provided, which has: (i) a first gate electrode in an electrically floating state, at least a part of which confronts a channel region of a semiconductor device and which is separated by an insulating layer from the channel region; (ii) a second gate electrode (i.e., a control electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode; and (iii) a third gate electrode (i.e., an erasing electrode), at least a part of which confronts the first gate electrode and is separated by an insulating layer from the first gate electrode. The insulating layer, separating at least a part of the erasing electrode from the first gate electrode, has a thickness (usually 50 to 300 A) sufficient to allow the passage of charges from the first gate electrode to the erasing electrode through a tunneling effect, thereby discharging the first gate electrode.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: September 20, 1983
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka
  • Patent number: 4326213
    Abstract: A polycrystalline silicon is used for a resistor element of a semiconductor device instead of a conventional, diffused resistor or a channel resistor, in which the channel resistance of an MOS transistor is utilized as the resistor. The length of a polycrystalline silicon layer for the resistor element is predetermined by the other polycrystalline silicon layer, formed above the resistor element. The structure of the semiconductor device according to the present invention is suited for a high density integrated circuit.
    Type: Grant
    Filed: November 29, 1978
    Date of Patent: April 20, 1982
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka
  • Patent number: 4271582
    Abstract: In a method of smoothing the edges of a window through a PSG film of a semiconductor device, a masking film is provided under the PSG film, so as to prevent impurities of the PSG film from penetrating into semiconductor substrate during the heating of the PSG film for the smoothing of the edges. A masking film, for example, an Si.sub.3 N.sub.4 film, does not, however, inhibit the penetration of hydrogen gas, which can improve the properties of an MIS semiconductor device.
    Type: Grant
    Filed: August 29, 1979
    Date of Patent: June 9, 1981
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shirai, Izumi Tanaka, Shinpei Tanaka, Keiji Nishimoto