Patents by Inventor J. Kawamura
J. Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210074345Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: SCOTT J. DERNER, CHRISTOPHER J. KAWAMURA
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Patent number: 10910038Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.Type: GrantFiled: April 30, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Charles L. Ingalls, Tae H. Kim
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Patent number: 10910379Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 15, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Patent number: 10896717Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.Type: GrantFiled: December 28, 2018Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Christopher J. Kawamura
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Patent number: 10885964Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.Type: GrantFiled: September 12, 2019Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Christopher J. Kawamura
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Publication number: 20200411076Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Inventors: Tae H. Kim, Christopher J. Kawamura
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Patent number: 10872650Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.Type: GrantFiled: May 29, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Christopher J. Kawamura
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Patent number: 10867661Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.Type: GrantFiled: April 30, 2019Date of Patent: December 15, 2020Assignee: Micron Technology, Inc.Inventors: Tae H. Kim, Christopher J. Kawamura
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Patent number: 10861787Abstract: Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.Type: GrantFiled: August 7, 2019Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Mitsunari Sukekawa, Christopher J. Kawamura
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Patent number: 10854276Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.Type: GrantFiled: August 20, 2018Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Scott J. Derner
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Publication number: 20200357454Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: SCOTT J. DERNER, CHRISTOPHER J. KAWAMURA
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Publication number: 20200349998Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Tae H. Kim, Christopher J. Kawamura
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Publication number: 20200349999Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.Type: ApplicationFiled: April 30, 2019Publication date: November 5, 2020Inventors: Christopher J. Kawamura, Charles L. Ingalls, Tae H. Kim
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Patent number: 10818342Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.Type: GrantFiled: August 20, 2018Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Scott J. Derner
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Patent number: 10783951Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.Type: GrantFiled: August 20, 2018Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Scott J. Derner
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Patent number: 10783948Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.Type: GrantFiled: May 29, 2019Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Christopher J. Kawamura
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Publication number: 20200295008Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Patent number: 10622057Abstract: A sensing system can read from a memory cell configured to store a data bit and to produce a differential signal indicating a data state of the memory cell. The data state can be selected from three data states. An example of the system can include a pair of bit lines, a pair of sense amplifiers (SAs), and a data output circuit. The bit lines are coupled to the memory cell to receive the differential signal. The SAs are each independently coupled to the bit lines through an isolation circuit. The data output circuit can receive outputs from the SAs and indicate the data state of the memory cell based on the outputs.Type: GrantFiled: April 26, 2018Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Charles L. Ingalls, Scott J. Derner
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Patent number: 10535399Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.Type: GrantFiled: September 21, 2018Date of Patent: January 14, 2020Assignee: Micron Technology, Inc.Inventors: Christopher J. Kawamura, Scott J. Derner
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Publication number: 20200005850Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: SCOTT J. DERNER, CHRISTOPHER J. KAWAMURA