Abstract: A MEMS component includes, on a substrate, component structures, contact areas connected to the component structures, metallic column structures seated on the contact areas, and metallic frame structures surrounding the component structures. A cured resist layer is seated on frame structure and column structures such that a cavity is enclosed between substrate, frame structure and resist layer. A structured metallization is provided directly on the resist layer or on a carrier layer seated on the resist layer. The structured metallization includes at least external contacts of the component and being electrically conductively connected both to metallic structures and to the contact areas of the component structures.

Abstract: The invention relates to a component and a method for producing said component. The component comprises a substrate (S), a chip (CH), a frame (MF), which is connected to the substrate (S) and on which the chip (CH) bears. A metallic closure layer (ML) encompasses the frame (MF), the substrate (S) and the chip (CH) such that a volume enclosed by the substrate (S), the chip (CH) and the frame (MF) is hermetically sealed.

Abstract: The present invention relates to a method for producing a sensor (SEN), comprising the steps of arranging a sensor element (SE) on a carrier (TR), arranging a cover (AF) on the sensor element (SE), wherein the sensor element (SE) is enclosed between the cover (AF) and the carrier (TR), adhesively bonding a carrier film (TF) onto the cover (AF), and producing an opening (SO) in the carrier film (TF) and the cover (AF), wherein the openings (SO) in the carrier film (TF) and the cover (AF) at least partly overlap.

Abstract: A component includes a substrate, a chip, and a frame. The frame, the substrate, and the chip enclose a volume. A metal sealing layer is provided which is designed to hermetically seal the volume. The metal sealing layer has a hardened liquid metal or a hardened liquid metal alloy.

Abstract: Frames (3) applied on a wafer (1) are leveled and covered with a covering film, such that gas-tight housings are formed for component structures (5), in particular for filter or MEMS structures. Inner columns (4) can be provided for supporting the housing and for the ground connection; outer columns (4) can be provided for the electrical connection and are connected to the component structures by means of conductor tracks (6) that are electrically insulated from the frames (3).

Abstract: A hermetic wafer-level package composed of two piezoelectric wafers, preferably identical in terms of material, and a production method therefor are presented. The electrical and mechanical connection between the two wafers is accomplished with frame structures and pillars, the partial structures of which, distributed between two wafers, are wafer-bonded with the aid of connecting layers.

Abstract: The invention relates to a cased electrical component comprising a carrier substrate (10), a spring device (20), which is arranged on the carrier substrate (10), a chip (30), which on a first side (31) of the chip is coupled to the spring device (20), and a cover element (100), which is arranged on the carrier substrate (10). The cover element (100) is arranged over the chip (20) such that the cover element (100) is in contact with the chip (30) at least on a second side (32) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

Abstract: The invention relates to a component and a method for producing said component. The component comprises a substrate (S), a chip (CH), a frame (MF), which is connected to the substrate (S) and on which the chip (CH) bears. A metallic closure layer (ML) encompasses the frame (MF), the substrate (S) and the chip (CH) such that a volume enclosed by the substrate (S), the chip (CH) and the frame (MF) is hermetically sealed.

Abstract: A component includes a substrate, a chip and a frame. The frame is bonded to the substrate and the chip rests on the frame. A sealing layer on parts of the frame and the chip is designed to hermetically seal a volume enclosed by the substrate, the chip and the metal frame.

Abstract: Frames (3) applied on a wafer (1) are leveled and covered with a covering film, such that gas-tight housings are formed for component structures (5), in particular for filter or MEMS structures. Inner columns (4) can be provided for supporting the housing and for the ground connection; outer columns (4) can be provided for the electrical connection and are connected to the component structures by means of conductor tracks (6) that are electrically insulated from the frames (3).

Abstract: A component having a multilayer solderable or bondable connecting surface on a substrate is proposed, which, in addition to the electrically conductive pad metallization and the UBM metallization also has an electrically conductive stress compensation layer that is arranged between the substrate and the pad metallization or between the pad metallization and the UBM metallization. The insensitivity to stress of the connecting metallization is achieved by means of a stress compensation layer whose modulus of elasticity is less than that of the UBM metallization.

Abstract: A component includes a carrier substrate having a coefficient of thermal expansion ?p and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion ?1 in a first direction x1 and a first expansion difference, ??1 equal to the absolute value of ?p??1. The chip also has a second coefficient of thermal expansion ?2 in a second direction x2 and a second expansion difference ??2 is equal to the absolute value of ?p??2,. The bumps are arranged such that a first distance, ?x1, corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x1 is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x2.

Abstract: The present invention relates to an encapsulated component that includes a carrier substrate and at least one chip positioned on the top of the carrier substrate and electrically connected to it by means of electrically conductive connections. The encapsulation of the chip is accomplished with a seal or dielectric layer. As a result of differing coefficients of expansion of the seal or dielectric layer and the electrically conductive connections, with changing temperatures stresses occur in the electrically conductive connections, which can lead to cracks, breaks and even to interruption of the electrically conductive connections.

Abstract: A component includes a carrier substrate having a coefficient of thermal expansion ?p and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion ?1 in a first direction x1 and a first expansion difference, ??1 equal to the absolute value of ?p??1. The chip also has a second coefficient of thermal expansion ?2 in a second direction x2 and a second expansion difference ??2 is equal to the absolute value of ?p??2,. The bumps are arranged such that a first distance, ?x1, corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x1 is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x2.

Abstract: For simpler and safer encapsulation of components, it is proposed to generate the connection between a chip and a carrier substrate by means of bump connections that are sunk into recesses on the carrier substrate. The component thereby lies directly on the carrier substrate, in particular on a frame circumscribing the component structures on the chip.