Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

Abstract: A non-pneumatic tire includes an annular inner ring, an annular outer ring, and a support structure extending from the annular inner ring to the annular outer ring. The support structure includes a plurality of spokes, webbing, cells, or other open-sided support structure. The tire includes a splash control band protruding from a side of the tire. The splash control band circumscribes a rotation axis of the tire and includes a surface facing the rotation axis. The surface can be continuous, angled, concave, and polygonal. The splash control band controls splashing of debris that accumulates within the support structure.

Abstract: This invention relates to novel whitening agents for cellulosic substrates. The whitening agents are comprised of at least two components: at least one chromophore component and at least one polymeric component. Suitable chromophore components generally fluoresce blue, red, violet, or purple color when exposed to ultraviolet light, or they may absorb light to reflect these same shades. The whitening agents are further characterized by having a dispersion component value of the Hansen Solubility Parameter of less than or equal to about 17 MPa0.5. This invention also relates to laundry care compositions including but not limited to liquid and/or powder laundry detergent formulations and rinse added fabric softening (RAFS) compositions that comprise such whitening agents.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: A rim assembly for a non-pneumatic tire has at least two rim components including: a first rim component having a first rim flange and a first lip, and a second rim component having a second rim flange and a second lip. The rim assembly further includes a plurality of lateral rim component support structures configured to extend through a plurality of openings of a tire support structure. The rim assembly also includes a first plurality of fasteners securing the plurality of lateral rim component support structures to the first rim flange, and a second plurality of fasteners securing the plurality of lateral rim component support structures to the second rim flange.

Abstract: The invention includes embodiments of a system and method for managing a sales campaign. The system and methods disclosed herein are particularly useful in the context of an entity in the business of direct marketing and sales.

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory.

Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

Abstract: In some embodiments, a method and apparatus, as well as an article, may operate to determine downhole properties based on detected optical signals. An optical detection apparatus can include an optical detector including a superconducting nanowire single photon detector (SNSPD) for detecting light received at an input section of fiber optic cable. The optical detection apparatus can further include a cryogenic cooler configured to maintain the temperature of a light-sensitive region of the SNSPD within a superconducting temperature range of the SNSPD. Downhole properties are measured based on detected optical signals received at the optical detection apparatus. Additional apparatus, systems, and methods are disclosed.

Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit.

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: Techniques are provided for tomographic imaging with sub-beam resolution and spectral enhancement. A system implementing the techniques according to an embodiment includes a target structure comprising one or more selected materials nanopatterned on a first surface of the target structure in a selected arrangement. The system also includes a primary particle beam source to provide a particle beam incident on an area of the first surface of the target structure, the area encompassing one or more of the nanopatterned materials, such that the materials generate characteristic X-rays in response to the primary beam. The system further includes a spectral energy detector (SED) to perform individual photon counting and spectral analysis of the characteristic X-rays and estimate attenuation properties of the imaged sample. The sample is positioned both adjacent to a second surface of the target structure, opposite the first surface, and between the target structure and the SED.

Abstract: An optical detection system for analyzing a fluid sample including a light source configured to emit a light beam to interact with the sample to form a spectrum, an optical fiber to transmit the spectrum, an array of single-photon detectors (SPDs), and wherein each SPD is configured to receive and is tunable to analyze spectral characteristics of the spectrum across a spectral range.

Abstract: A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

Abstract: A sensor layer system precursor (48) configured for forming a sensor layer system (26), the sensor layer system (26) being configured for absorbing hydrogen, includes a sensing layer precursor (42) made from a sensing layer precursor material that consists of: 20% by weight to 90% by weight palladium or palladium alloy, the palladium alloy consisting of palladium and at least one palladium alloy partner chosen from group VIIIB, wherein the amount-of-substance fraction of palladium is at least 85% and the sum of the amount-of-substance fractions of all palladium alloy partners contained in the palladium alloy is at most 15% with respect to the whole amount of substance of the palladium alloy, respectively; 10% by weight to 80% by weight sacrificial metal, the sacrificial metal being at least as electropositive as palladium and each palladium alloy partner and/or the sacrificial metal being selectively transformable by a chemical process into a soluble and/or ionic form; remainder unavoidable impurities; and op

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: A non-pneumatic tire includes a plurality of axially adjacent wheel portions. Each wheel portion has an inner ring, an outer ring, and a flexible, interconnected web extending between the inner ring and the outer ring. The flexible, interconnected web includes a plurality of web sectors disposed circumferentially about the tire to form a generally annular web. Each of the plurality of web sectors is hingedly connected to a pair of oppositely adjacent web sectors.

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.