Patents by Inventor J. Xu

J. Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combinations of TGFBeta and COX-2 Inhibitors and Methods for Their Therapeutic Application
    Publication number: 20130225655
    Abstract: The present invention provides compositions and methods for using combinations of TGF?1 and Cox-2 inhibitors and TGF?1 and Hoxb13 inhibitors for the treatment of various medical conditions, including skin scaring due to trauma wounds and surgery, corneal and retina scaring due to injury and surgery, internal organ scaring due to injury and surgery, heart tissue scaring due to heart attack and surgery, and lung, liver, and kidney fibrosis due to inflammation and injury. One example is to use siRNA inhibitors to silence TGF?1 and Cox-2 at the same time, resulting in significant less scar formation.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 29, 2013
    Inventors: Patrick Y. Lu, Vera Simonenko, David Evans, John J. Xu
  • Method of manufacturing source/drain structures
    Patent number: 8501570
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Jeff J. Xu, Ming-Jie Huang, Yimin Huang, Zhiqiang Wu, Min Cao
  • Method of making a FinFET device
    Patent number: 8497177
    Abstract: A method for fabricating a fin field-effect transistor (FinFET) device includes providing a substrate having a first fin at a first location, and epitaxially growing a second fin on the substrate at the first location. The epitaxial growth is performed at a first temperature. The method further includes performing a thermal annealing at a second temperature in oxygen ambient on the substrate with the second fin thereon to grow an interface wrapping over the second fin. The second temperature is higher than the first temperature.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huicheng Chang, Jeff J. Xu, Hung-Ta Lin, Chun-Feng Nieh
  • Method for fabricating a strained structure
    Patent number: 8497528
    Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Method for reducing interfacial layer thickness for high-k and metal gate stack
    Patent number: 8470659
    Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: June 25, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    Publication number: 20130154685
    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Irene J. Xu
  • Dual Targeted siRNA Therapeutics for Treatment of Diabetic Retinopathy and Other Ocular Neovascularization Diseases
    Publication number: 20130123330
    Abstract: The present invention relates to compositions and methods for treating diabetic retinopathy and other ocular neovascularization diseases. In one embodiment, the composition comprises at least two different siRNA duplexes and a pharmaceutically acceptable carrier. One of the duplexes binds to an mRNA molecule that encodes VEGF, and the other binds to an mRNA molecule that encodes VEGFR2. In another embodiment, the composition further comprises an siRNA duplex that binds to an mRNA molecule that encodes TGF?1.
    Type: Application
    Filed: July 15, 2012
    Publication date: May 16, 2013
    Inventors: Patrick Y. Lu, John J. Xu, Alan Y. Lu
  • Method of forming epi film in substrate trench
    Patent number: 8415718
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • METAL GATE DEVICE WITH LOW TEMPERATURE OXYGEN SCAVENGING
    Publication number: 20130078779
    Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jeff J. Xu
  • SEMICONDUCTOR DEVICE WITH STRAINED CHANNELS INDUCED BY HIGH-K CAPPING METAL LAYERS
    Publication number: 20130075826
    Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jeff J. Xu
  • Techniques Providing Metal Gate Devices with Multiple Barrier Layers
    Publication number: 20130056836
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Da-Yuan Lee, Kuan-Yuan Hsu, Jeff J. Xu
  • Fin-like field effect transistor (FinFET) device and method of manufacturing same
    Patent number: 8367498
    Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu
  • Non-uniformity reduction in semiconductor planarization
    Patent number: 8367534
    Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Jeff J. Xu
  • SELF-ALIGNED SOURCE AND DRAIN STRUCTURES AND METHOD OF MANUFACTURING SAME
    Publication number: 20130017660
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ziwei Fang, Ying Zhang, Jeff J. Xu
  • METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK
    Publication number: 20120322253
    Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi YAO, Chun-Hu CHENG, Chen-Yi LEE, Jeff J. XU, Clement Hsingjen WANN
  • Metal gate stress film for mobility enhancement in FinFET device
    Patent number: 8334570
    Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeff J. Xu, Clement H. Wann, Chi Cheh Yeh, Chi-Sheng Chang
  • Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
    Patent number: 8304841
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeff J. Xu, Cheng-Tung Lin, Hsiang-Yi Wang, Wen-Chin Lee, Betty Hsieh
  • Method for reducing interfacial layer thickness for high-K and metal gate stack
    Patent number: 8268683
    Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Method of fabrication of a semiconductor device having reduced pitch
    Patent number: 8241823
    Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
  • SOURCE/DRAIN STRESSOR HAVING ENHANCED CARRIER MOBILITY AND METHOD FOR MANUFACTURING SAME
    Publication number: 20120138897
    Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hsiang Lin, Jeff J. Xu, Pang-Yen Tsai