Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract: After sequentially forming an insulating layer and a capping dielectric layer having a higher density than the insulating layer, a chemical mechanical polishing (CMP) process is performed to prevent scratch from being formed on the surface of the insulating layer at the early stage of the CMP process. Thus, a semiconductor device with improved reliability is achieved.

Abstract: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

Abstract: There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole.

Abstract: A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract: A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

Abstract: A fixed abrasive polishing pad includes a base and a plurality of polishing layers on the base, wherein each polishing layer includes abrasive particles and apertures in a polishing surface of the polishing layer.