Patents by Inventor Ja-Eung Koo
Ja-Eung Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791173Abstract: Substrate cleaning equipment includes a substrate holder which supports a substrate, a swing body, a head, a first cleaning liquid supply structure, and a second cleaning liquid supply structure. The swing body moves along a sweep line on a main surface of the substrate. The head is coupled to the swing body and includes a pad attachment surface facing the substrate holder. The first cleaning liquid supply structure is coupled to the swing body and sprays a first cleaning liquid onto the main surface of the substrate. The second cleaning liquid supply structure sprays a second cleaning liquid onto the main surface of the substrate. A buffing pad is attached to the pad attachment surface.Type: GrantFiled: January 13, 2020Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Hoon Choi, Ja Eung Koo, No Ui Kim, Hyun Kyo Seo, Tae Min Earmme, Bo Un Yoon, Youn Cheol Jeong
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Patent number: 11648644Abstract: A polishing pad conditioning apparatus according to an example embodiment of the present inventive concept includes an apparatus body, a pivot arm provided on the apparatus body and including a housing having an internal space and provided at a distal end portion of the pivot arm and a head unit disposed at the distal end portion of the pivot arm. The head unit includes: a rotary motor provided in the internal space of the housing, the rotary motor including a rotary shaft; a foreign material blocking member connected to the rotary shaft; a disk holder connected to the rotary shaft; and a conditioning disk coupled to the disk holder. The foreign material blocking member includes a fluid flow groove configured to guide a movement of fluid for preventing foreign objects from entering the housing on an outer surface of the foreign material blocking member.Type: GrantFiled: July 22, 2019Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Seok Lee, Ja Eung Koo, Kuen Byul Kim, Jeong Min Na, Chang Gil Ryu, Hyeon Dong Song, Young Seok Jang, Jin Suk Hong
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Publication number: 20230053379Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device includes comprising a gate structure including a gate electrode and a gate capping pattern on an upper surface of the gate electrode; a source/drain pattern on at least one side of the gate structure; and a source/drain contact on and connected with an upper surface of the source/drain pattern, the source/drain contact extending along a sidewall of the gate electrode, wherein an upper surface of the source/drain contact includes a convex curved surface.Type: ApplicationFiled: March 3, 2022Publication date: February 23, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Seung Hoon CHOI, Ja Eung KOO, Il Young YOON
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Patent number: 11361995Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.Type: GrantFiled: January 12, 2021Date of Patent: June 14, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Hoon Choi, Ja-Eung Koo, Kwan-Sik Kim, Dong-Chan Kim, Il-Young Yoon, Man-Geun Cho
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Patent number: 11189572Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.Type: GrantFiled: April 15, 2019Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Tae Lee, Seung-Hoon Choi, Min-Chan Gwak, Ja-Eung Koo, Sang-Hyun Park
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Publication number: 20210166976Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.Type: ApplicationFiled: January 12, 2021Publication date: June 3, 2021Inventors: Seung-Hoon Choi, Ja-Eung Koo, Kwan-Sik Kim, Dong-Chan Kim, Il-Young Yoon, Man-Geun Cho
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Patent number: 10910266Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.Type: GrantFiled: March 7, 2019Date of Patent: February 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Hoon Choi, Ja-Eung Koo, Kwan-Sik Kim, Dong-Chan Kim, Il-Young Yoon, Man-Geun Cho
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Publication number: 20200303218Abstract: Substrate cleaning equipment includes a substrate holder which supports a substrate, a swing body, a head, a first cleaning liquid supply structure, and a second cleaning liquid supply structure. The swing body moves along a sweep line on a main surface of the substrate. The head is coupled to the swing body and includes a pad attachment surface facing the substrate holder. The first cleaning liquid supply structure is coupled to the swing body and sprays a first cleaning liquid onto the main surface of the substrate. The second cleaning liquid supply structure sprays a second cleaning liquid onto the main surface of the substrate. A buffing pad is attached to the pad attachment surface.Type: ApplicationFiled: January 13, 2020Publication date: September 24, 2020Inventors: SEUNG HOON CHOI, JA EUNG KOO, NO UI KIM, HYUN KYO SEO, TAE MIN EARMME, BO UN YOON, YOUN CHEOL JEONG
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Publication number: 20200206870Abstract: A polishing pad conditioning apparatus according to an example embodiment of the present inventive concept includes an apparatus body, a pivot arm provided on the apparatus body and including a housing having an internal space and provided at a distal end portion of the pivot arm and a head unit disposed at the distal end portion of the pivot arm. The head unit includes: a rotary motor provided in the internal space of the housing, the rotary motor including a rotary shaft; a foreign material blocking member connected to the rotary shaft; a disk holder connected to the rotary shaft; and a conditioning disk coupled to the disk holder. The foreign material blocking member includes a fluid flow groove configured to guide a movement of fluid for preventing foreign objects from entering the housing on an outer surface of the foreign material blocking member.Type: ApplicationFiled: July 22, 2019Publication date: July 2, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun Seok LEE, Ja Eung KOO, Kuen Byul KIM, Jeong Min NA, Chang Gil RYU, Hyeon Dong SONG, Young Seok JANG, Jin Suk HONG
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Publication number: 20200058549Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.Type: ApplicationFiled: March 7, 2019Publication date: February 20, 2020Inventors: SEUNG-HOON CHOI, JA-EUNG KOO, KWAN-SIK KIM, DONG-CHAN KIM, IL-YOUNG YOON, MAN-GEUN CHO
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Publication number: 20200027842Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.Type: ApplicationFiled: April 15, 2019Publication date: January 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Tae LEE, Seung-Hoon CHOI, Min-Chan GWAK, Ja-Eung KOO, Sang-Hyun PARK
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Patent number: 10056466Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.Type: GrantFiled: June 24, 2016Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jae Lee, Ja-Eung Koo, Ho-Young Kim, Yeong-Bong Park, Il-Su Park, Bo-Un Yoon, Il-Young Yoon, Youn-Su Ha
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Patent number: 10032890Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.Type: GrantFiled: November 28, 2016Date of Patent: July 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hwan Yim, Yeon-Tack Ryu, Joo-Cheol Han, Ja-Eung Koo, No-Ul Kim, Ho-Young Kim, Bo-Un Yoon
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Patent number: 9870950Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.Type: GrantFiled: December 7, 2016Date of Patent: January 16, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Sun Hwang, Ja-Eung Koo, Jong-Hyung Park, Ho-Young Kim, Leian Bartolome, Bo-Un Yoon, Hyoung-Bin Moon
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Publication number: 20170170072Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.Type: ApplicationFiled: December 7, 2016Publication date: June 15, 2017Inventors: CHANG-SUN HWANG, JA-EUNG KOO, JONG-HYUNG PARK, HO-YOUNG KIM, LEIAN BARTOLOME, BO-UN YOON, HYOUNG-BIN MOON
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Publication number: 20170162675Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.Type: ApplicationFiled: November 28, 2016Publication date: June 8, 2017Inventors: Jun-Hwan YIM, Yeon-Tack RYU, Joo-Cheol HAN, Ja-Eung KOO, No-Ul KIM, Ho-Young KIM, Bo-Un YOON
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Publication number: 20170040436Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.Type: ApplicationFiled: June 24, 2016Publication date: February 9, 2017Inventors: Seung-Jae LEE, Ja-Eung KOO, Ho-Young KIM, Yeong-Bong PARK, Il-Su PARK, Bo-Un YOON, Il-Young YOON, Youn-Su HA
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Patent number: 7595253Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.Type: GrantFiled: May 8, 2007Date of Patent: September 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: II-Young Yoon, Hong-Jae Shin, Nae-In Lee, Jae-Ouk Choo, Ja-Eung Koo
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Publication number: 20080132030Abstract: After sequentially forming an insulating layer and a capping dielectric layer having a higher density than the insulating layer, a chemical mechanical polishing (CMP) process is performed to prevent scratch from being formed on the surface of the insulating layer at the early stage of the CMP process. Thus, a semiconductor device with improved reliability is achieved.Type: ApplicationFiled: December 4, 2007Publication date: June 5, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Young YOON, Dong-Suk SHIN, Jae-Ouk CHOO, Ja-Eung KOO
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Publication number: 20080081406Abstract: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.Type: ApplicationFiled: May 18, 2007Publication date: April 3, 2008Inventors: Jae-ouk Choo, II-young Yoon, Seo-woo Nam, Ja-eung Koo