Abstract: There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole.

Abstract: A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract: A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

Abstract: A fixed abrasive polishing pad includes a base and a plurality of polishing layers on the base, wherein each polishing layer includes abrasive particles and apertures in a polishing surface of the polishing layer.

Abstract: A flexible membrane for a polishing head and a chemical mechanical polishing (CMP) apparatus having the same are provided. The flexible membrane for a polishing head includes a compressing plate having a first face and a second face opposite to the first face. The first face of the compressing plate holds a substrate with a vacuum provided thereto and compresses the substrate on a polishing pad. The second face of the compressing plate is combined with a supporter of the polishing head. The second face and the supporter define a space to which the vacuum for holding the substrate and a first pneumatic pressure for compressing the substrate are applied. A dividing member combined with the supporter is formed on the second face. The dividing member divides the space into at least two regions. A pneumatic pressure-introducing portion is formed at the dividing member. A second pneumatic pressure is provided to the compressing plate through the pneumatic pressure-introducing portion.

Abstract: There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole.

Abstract: An interconnection structure and a method of fabricating the same are provided. The interconnection structure includes an interlayer insulating layer having a structure comprising a via hole structure or a trench-shaped line structure. A conformal metal diffusion barrier layer is disposed inside the via hole structure or the trench-shaped line structure of the interlayer insulating layer. An insulating diffusion barrier spacer is disposed to cover the metal diffusion barrier layer on the sidewalls of the via hole structure or the trench-shaped line structure of the interlayer insulating layer. In addition, a copper interconnection is disposed to fill the inside of the via hole structure or the trench-shaped line structure of the interlayer insulating layer.

Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor.

Abstract: A flexible membrane for a polishing head and a chemical mechanical polishing (CMP) apparatus having the same are provided. The flexible membrane for a polishing head includes a compressing plate having a first face and a second face opposite to the first face. The first face of the compressing plate holds a substrate with a vacuum provided thereto and compresses the substrate on a polishing pad. The second face of the compressing plate is combined with a supporter of the polishing head. The second face and the supporter define a space to which the vacuum for holding the substrate and a first pneumatic pressure for compressing the substrate are applied. A dividing member combined with the supporter is formed on the second face. The dividing member divides the space into at least two regions. A pneumatic pressure-introducing portion is formed at the dividing member. A second pneumatic pressure is provided to the compressing plate through the pneumatic pressure-introducing portion.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.