Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.

Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.

Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.

Abstract: An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.

Abstract: An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.

Abstract: A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N?1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N?2 bit analog-to-digital conversion result by combining converted upper N?1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.

Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.

Abstract: A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N?1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N?2 bit analog-to-digital conversion result by combining converted upper N?1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N?M (1?M<N, M is the natural number) bits in a case where the input voltage is larger than the first voltage, and a signal correction unit configured to: generate a corrected digital signal based on a boundary value and the digital signal, in a case where a value of the digital signal is larger than the boundary value and the input voltage is smaller than the first voltage.

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N?M (1?M<N, M is the natural number) bits in a case where the input voltage is larger than the first voltage, and a signal correction unit configured to: generate a corrected digital signal based on a boundary value and the digital signal, in a case where a value of the digital signal is larger than the boundary value and the input voltage is smaller than the first voltage.

Abstract: The analog-to-digital converter includes a signal processing unit generating an operational amplifier output voltage in response to an input voltage and a DAC output voltage in a first period and generating the operational amplifier output voltage in response to a feedbacked operational amplifier output voltage and the DAC output voltage in a second period; a control unit generating a DAC control signal by comparing the operational amplifier output voltage with a first reference voltage to obtain high order M-bits of data in the first period, and generating the DAC control signal by comparing the operational amplifier output voltage with second and third reference voltages to obtain low order N-bits of data in the second period; and a digital analog converter generating the DAC output voltage in response to the DAC control signal.

Abstract: An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1st to Nth capacitors having one ends connected to the input node, respectively; and 1st to N?1th voltage selection units corresponds to the 2nd to Nth capacitors, respectively and applies one of a voltages of a 1st node, a 2nd node, and the comparison voltage to the other ends of the corresponding capacitors. An input signal is sampled to the input node, the 1st to N?1th voltage selection units select one of the voltages of the 2 nodes and convert a part of the input signal into a 1st digital signal, and the 1st to N?1th voltage selection units select one of the voltages of the 2 nodes and convert the remaining part of the input signal into a 2nd digital signal.

Abstract: An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1st to Nth capacitors having one ends connected to the input node, respectively; and 1st to N?1th voltage selection units corresponds to the 2nd to Nth capacitors, respectively and applies one of a voltages of a 1st node, a 2nd node, and the comparison voltage to the other ends of the corresponding capacitors. An input signal is sampled to the input node, the 1st to N?1th voltage selection units select one of the voltages of the 2 nodes and convert a part of the input signal into a 1st digital signal, and the 1st to N?1th voltage selection units select one of the voltages of the 2 nodes and convert the remaining part of the input signal into a 2nd digital signal.

Abstract: The analog-to-digital converter includes a signal processing unit generating an operational amplifier output voltage in response to an input voltage and a DAC output voltage in a first period and generating the operational amplifier output voltage in respose to a feedbacked operational amplifier output voltage and the DAC output voltage in a second period; a control unit generating a DAC control signal by comparing the operational amplifier output voltage with a first reference voltage to obtain high order M-bits of data in the first period, and generating the DAC control signal by comparing the operational amplifier output voltage with second and third reference voltages to obtain low order N-bits of data in the second period; and a digital analog converter generating the DAC output voltage in response to the DAC control signal.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Abstract: Semiconductor memory device with internal voltage generating circuit and method for operating the same includes a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and an active signal; and an auxiliary pumping circuit configured to perform the pumping operation in response to the pumping determining signal and a bank active pulse signal.

Abstract: An internal voltage generator is capable of supplying a stable internal voltage regardless of an unstable external voltage. The internal voltage includes a first level detecting unit configured to detect a voltage level of the internal voltage and output an output power detecting signal, an oscillating unit configured to produce a periodical signal in response to the output power detecting signal, a second level detecting unit configured to detect a voltage level of an external voltage and output a driving power detecting signal, a dividing unit configured to selectively divide the periodical signal in response to the driving power detecting signal and output a divided signal, and a charge pumping unit configured to provide the internal voltage by pumping the external voltage in response to the divided signal.

Abstract: Semiconductor memory device with internal voltage generating circuit and method for operating the same includes a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and an active signal; and an auxiliary pumping circuit configured to perform the pumping operation in response to the pumping determining signal and a bank active pulse signal.

Abstract: A voltage pumping device is disclosed. The device may include a voltage level detector for detecting a level of a voltage fed back thereto and generating a voltage pumping enable signal according to the detected voltage level, an oscillator for operating in response to the voltage pumping enable signal and generating a desired pulse signal in a normal operation mode, a clock supply controller for receiving an external clock signal, operating in response to the voltage pumping enable signal and outputting the external clock signal in a low-power operation mode, and a voltage pump for performing a voltage pumping operation in response to the pulse signal from the oscillator in the normal operation mode and performing the voltage pumping operation in response to the clock signal from the clock supply controller in the low-power operation mode.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.