Abstract: Disclosed is an apparatus for generating an elevated voltage that compares an external supply voltage with a reference voltage, and performs voltage pumping using either the reference voltage or the external supply voltage as an input voltage of a pumping unit.

Abstract: An internal voltage generator is capable of supplying a stable internal voltage regardless of an unstable external voltage. The internal voltage includes a first level detecting unit configured to detect a voltage level of the internal voltage and output an output power detecting signal, an oscillating unit configured to produce a periodical signal in response to the output power detecting signal, a second level detecting unit configured to detect a voltage level of an external voltage and output a driving power detecting signal, a dividing unit configured to selectively divide the periodical signal in response to the driving power detecting signal and output a divided signal, and a charge pumping unit configured to provide the internal voltage by pumping the external voltage in response to the divided signal.

Abstract: A voltage level detection circuit is disclosed. The voltage level detection circuit comprises a pull-up unit including a plurality of pull-up devices, each for supplying an internal voltage in response to a signal resulting from a logic operation of a voltage up control signal and a voltage down control signal, a voltage division unit including a plurality of voltage dividers, each for dividing the internal voltage from a corresponding one of the pull-up device, a switching unit including a plurality of switching devices, each for switching and supplying an output voltage from a corresponding one of the voltage dividers to an output node in response to a signal resulting from a logic operation of the voltage up control signal and voltage down control signal, and a comparator for comparing the voltage at the output node with a predetermined reference voltage and outputting a voltage pumping enable signal according to a result of the comparison.

Abstract: Disclosed is an apparatus for generating an elevated voltage that compares an external supply voltage with a reference voltage, and performs voltage pumping using either the reference voltage or the external supply voltage as an input voltage of a pumping unit.

Abstract: An apparatus, included in a semiconductor memory device, for generating a bank control signal, includes a logic block for receiving an internal precharge signal and a power-up signal and outputting a first signal; and a latch block for latching an internal active signal and the first signal in order to generate the bank control signal.

Abstract: The present invention relates to a refresh oscillator, and more specifically, to a refresh oscillator in which an oscillation cycle can vary according to variation in temperature of DRAM devices. According to the present invention, the refresh oscillator comprises a biasing circuit for generating a bias using a current mirror, a temperature compensation circuit for compensating for variation in the bias depending upon variation in temperature by controlling a resistance ratio, and an oscillator, which is driven by the bias compensated for by the temperature compensation circuit, thus generating an output signal that varies depending upon variation in temperature. Accordingly, since an oscillation cycle can be changed depending upon variation in temperature, the refresh oscillator can be applied to a design of all DRAM circuits for low power consumption.

Abstract: An apparatus, included in a semiconductor memory device, for generating a bank control signal, includes a logic block for receiving an internal precharge signal and a power-up signal and outputting a first signal; and a latch block for latching an internal active signal and the first signal in order to generate the bank control signal.

Abstract: Disclosed is a precharge apparatus in a semiconductor memory device and a precharge method using the same. The precharge apparatus includes a memory array in which a plurality of memory banks are divided into at least two memory groups, and a precharge all command decoder to generate at least two precharge signals according to a precharge command signal and an address signal, wherein the at least two precharge signals are each output with a time lag according to a control signal to precharge the ate least two memory groups with a time lag. Therefore, the peak current is distributed to reduce the power bouncing.