Patents by Inventor Ja Yol Lee
Ja Yol Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230119518Abstract: A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.Type: ApplicationFiled: October 14, 2022Publication date: April 20, 2023Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Ja Yol LEE
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Patent number: 10976409Abstract: Provided is frequency-modulated continuous wave generator. The frequency-modulated continuous wave generator includes a ramp signal generator configured to generate an analog ramp signal, a reference signal generator configured to generate a reference signal based on the analog ramp signal, a phase locked loop configured to output a control voltage based on the reference signal, and a voltage-controlled oscillator configured to generate a frequency-modulated continuous wave based on the control voltage. The ramp signal generator is further configured to generate the analog ramp signal based on a feedback signal based on the frequency-modulated continuous wave.Type: GrantFiled: November 20, 2017Date of Patent: April 13, 2021Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Bon Tae Koo
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Patent number: 10917046Abstract: Provided is an electronic circuit including a resonant circuit configured to output a resonance voltage having a resonance frequency to a first node, and an oscillation circuit configured to output an oscillation voltage having a level changed according to a first current and a second current based on the resonance voltage received from the first node, wherein the first current is delivered between a first voltage supply terminal and a second node in a first time period, the second current is delivered between the second node and a second voltage supply terminal in a second time period, and a sum of a length of the first time period and a length of the second time period corresponds to the resonance frequency.Type: GrantFiled: October 14, 2019Date of Patent: February 9, 2021Assignee: Electronics and Telecommunications Research InstituteInventor: Ja Yol Lee
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Patent number: 10819129Abstract: Provided is a battery charging system including a battery gauge configured to scale down to indicate a charging capacity of a battery, a charging mode switching unit configured to monitor a charging state of the battery gauge, switch a charging mode according to the charging state of the battery gauge, and charge the battery according to the switched charging mode, and a battery charging control unit configured to receive a charging current input to the battery gauge and a battery charging current input to the battery, and control the charging mode switching unit.Type: GrantFiled: March 23, 2018Date of Patent: October 27, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Bon Tae Koo
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Publication number: 20200119690Abstract: Provided is an electronic circuit including a resonant circuit configured to output a resonance voltage having a resonance frequency to a first node, and an oscillation circuit configured to output an oscillation voltage having a level changed according to a first current and a second current based on the resonance voltage received from the first node, wherein the first current is delivered between a first voltage supply terminal and a second node in a first time period, the second current is delivered between the second node and a second voltage supply terminal in a second time period, and a sum of a length of the first time period and a length of the second time period corresponds to the resonance frequency.Type: ApplicationFiled: October 14, 2019Publication date: April 16, 2020Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Ja Yol LEE
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Publication number: 20180278072Abstract: Provided is a battery charging system including a battery gauge configured to scale down to indicate a charging capacity of a battery, a charging mode switching unit configured to monitor a charging state of the battery gauge, switch a charging mode according to the charging state of the battery gauge, and charge the battery according to the switched charging mode, and a battery charging control unit configured to receive a charging current input to the battery gauge and a battery charging current input to the battery, and control the charging mode switching unit.Type: ApplicationFiled: March 23, 2018Publication date: September 27, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Ja Yol LEE, Bon Tae KOO
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Publication number: 20180143296Abstract: Provided is frequency-modulated continuous wave generator. The frequency-modulated continuous wave generator includes a ramp signal generator configured to generate an analog ramp signal, a reference signal generator configured to generate a reference signal based on the analog ramp signal, a phase locked loop configured to output a control voltage based on the reference signal, and a voltage-controlled oscillator configured to generate a frequency-modulated continuous wave based on the control voltage. The ramp signal generator is further configured to generate the analog ramp signal based on a feedback signal based on the frequency-modulated continuous wave.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol LEE, Bon Tae KOO
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Patent number: 9735788Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.Type: GrantFiled: June 17, 2016Date of Patent: August 15, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol Lee, Minjae Lee, Cheon Soo Kim, Jaehyun Kang, Junsoo Ko
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Publication number: 20170201259Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.Type: ApplicationFiled: September 23, 2016Publication date: July 13, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol LEE, Min Jae LEE, Cheon Soo KIM, Min Uk HEO
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Patent number: 9705515Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.Type: GrantFiled: September 23, 2016Date of Patent: July 11, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol Lee, Min Jae Lee, Cheon Soo Kim, Min Uk Heo
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Patent number: 9654119Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.Type: GrantFiled: June 16, 2016Date of Patent: May 16, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol Lee, Minjae Lee, Cheon Soo Kim, Jaehyun Kang, Minuk Heo
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Publication number: 20160373121Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.Type: ApplicationFiled: June 16, 2016Publication date: December 22, 2016Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ja Yol LEE, Minjae LEE, Cheon Soo KIM, Jaehyun KANG, Minuk HEO
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Publication number: 20160373115Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.Type: ApplicationFiled: June 17, 2016Publication date: December 22, 2016Applicant: Electronics and Telecommunications Research InstituteInventors: Ja Yol LEE, Minjae LEE, Cheon Soo KIM, Jaehyun KANG, Junsoo KO
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Patent number: 8797203Abstract: Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a first sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock.Type: GrantFiled: January 17, 2013Date of Patent: August 5, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Ja Yol Lee
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Patent number: 8432199Abstract: Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.Type: GrantFiled: December 2, 2011Date of Patent: April 30, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Seong-Do Kim, Hyun Kyu Yu
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Patent number: 8344772Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.Type: GrantFiled: November 30, 2010Date of Patent: January 1, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Seon Ho Han, Mi Jeong Park, Jang Hong Choi, Seong Do Kim, Hyun Kyu Yu
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Publication number: 20120161832Abstract: Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.Type: ApplicationFiled: December 2, 2011Publication date: June 28, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Seong-Do Kim, Hyun Kyu Yu
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Patent number: 8060020Abstract: An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed.Type: GrantFiled: December 1, 2009Date of Patent: November 15, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Seong Do Kim, Ja Yol Lee, Jae Hoon Shim, Hyun Kyu Yu
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Patent number: 8031009Abstract: A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.Type: GrantFiled: October 16, 2009Date of Patent: October 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Byung Hun Min, Ja Yol Lee, Seong Do Kim, Cheon Soo Kim, Hyun Kyu Yu
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Patent number: 8013641Abstract: There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.Type: GrantFiled: April 29, 2011Date of Patent: September 6, 2011Assignee: Electronics and Telecommunications Resarch InstittuteInventors: Ja Yol Lee, Seong Do Kim, Mun Yang Park, Cheon Soo Kim, Hyun Kyu Yu