Patents by Inventor Jacek Kowalski

Jacek Kowalski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6247033
    Abstract: The present invention relates to a random signal generator (10) comprising means (11, 12, 13) for converting an electronic noise (N, N1, N2) into a logic signal (RS) whose value depends on the random fluctuations of the electronic noise (N). According to one embodiment, the generator (10) comprises at least two delay lines (11, 12) having initially balanced time constants (T). The two delay lines (11, 12) receive a pulsed reference signal (Hr) at input and at least one of the delay lines (11, 12) receives an electronic noise (N1, N2) causing its time constant (T) to fluctuate (&Dgr;t). The temporal lag between the two pulsed signals (S1, S2) is detected by a circuit (13) delivering a logic signal (RS) whose value is a function of the relative lag between the two pulsed signals (S1, S2). Advantageously, the electronic noise (N1, N2) is a differential noise taken at two points (GND1, GND2) of a ground plane or two points (PV1, PV2) of an electrical supply plane.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: June 12, 2001
    Assignee: Inside Technologies
    Inventor: Jacek Kowalski
  • Patent number: 6212105
    Abstract: The present invention relates to a method for recording a binary word (BW) by means of electrically erasable and programmable type memory cells (Ci,j) organized in word lines (Wli), in which there are provided at least two word lines (WLi, XWLi) that can be erased or programmed independently of each other, the binary word is recorded in one of said word lines (XWLi) and, simultaneously, the other word line (XWLi) is erased. The invention is applied to the making of a memory system (10), a binary counter and an abacus counter that are secured.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 3, 2001
    Assignee: Inside Technologies
    Inventor: Jacek Kowalski
  • Patent number: 6152367
    Abstract: An authentication method for a wired-logic microcircuit mounted on a support and a microcircuit reading terminal. The microcircuit is provided with a memory which has data readable by the terminal. A secret code of the microcircuit is arranged in a region of the memory that is not readable by the terminal. The microcircuit generates an authentication code from the data in the memory that is readable by the terminal, the secret code and a random code. The terminal generates an authentication code from the data in the microcircuit memory that is readable by the terminal, a secret code provided to the terminal by a microcircuit user and random code, and the authentication code generated by the microcircuit is compared with the authentication code generated by the terminal.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: November 28, 2000
    Assignee: Inside Technologies
    Inventor: Jacek Kowalski
  • Patent number: 6058481
    Abstract: A logic machine and a circuit for producing an authentication code for authenticating smart cards which include a cycle of steps wherein a bit word is read out of a secret memory with a plurality of bit words, and words read out during previous cycles are combined. The result of the combination is used as a generator word for generating the address of the word to be read out in the next cycle.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: May 2, 2000
    Assignee: Inside Technologies
    Inventor: Jacek Kowalski
  • Patent number: 6038190
    Abstract: To reduce the risks of erroneous data writing into an electrically erasable and programmable non-volatile memory (10) (EEPROM) when a failure in the memory (10) voltage supply (Vcc) occurs during a programming or erasing operation, the memory (10) comprising means (30) of generating programming or erasing high voltage (Vpp), means (SW.sub.i, TI.sub.i,) are provided for maintaining the high voltage (Vpp) supply to the cells (C.sub.i,j) of the memory and capacity (Chv, CR.sub.2) of sufficient power to maintain the high voltage (Vpp) during the time required for the programming or erasing operation. The invention is useful particularly for EEPROM memories mounted on chip cards and electronic labels.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: March 14, 2000
    Assignee: Inside Technologies
    Inventors: Jacek Kowalski, Michel Martin
  • Patent number: 6034446
    Abstract: The invention concerns an integrated circuit comprising a resonant circuit (L,20) for receiving by electromagnetic induction an alternating voltage (V.sub.ac), the resonant circuit comprising at least one capacitance (C1-Ci) switchable by means of a programmed switch (11), the switch comprising a circuit breaker (7), a memory cell (6) and a circuit (31, 32, 33, 42) for controlling the circuit beaker (7), the control circuit being supplied by the alternating voltage (V.sub.ac) and arranged for opening or closing the circuit breaker (7) depending on the programming or the erasing status of the memory cell (6).
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: March 7, 2000
    Assignee: Inside Technologies
    Inventors: Jacek Kowalski, Michel Martin
  • Patent number: 6003777
    Abstract: A microcircuit with two contact and non-contact operating modes, including communication device (2) specific for the non-contact operating mode, communication device (3) specific for the contact operating mode, electronic circuit (4) common to both operating modes, a coil (L) for receiving an AC voltage (Va) by induction, a rectifier circuit (Pd) for rectifying the AC voltage (Va) to give a first microcircuit power supply voltage (Vcc1), at least one power supply contact (p1) for receiving a second microcircuit power supply voltage (Vcc2) a distribution line (5) for distributing the first (Vcc1), or second (Vcc2) power supply voltages, a switch circuit (6, 13) between the power supply contact (P1) and the distribution line (5), and controller (7, 8) for controlling the switch circuit, which controller (7, 8) are arranged to sense the AC voltage (Va) across the terminals of the coil (L), and close the switch circuit (6, 13) when the second power supply voltage (Vcc2) is present on the power supply contact, or
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: December 21, 1999
    Assignee: Inside Technologies
    Inventor: Jacek Kowalski
  • Patent number: 5982647
    Abstract: An integrated circuit (30) for non-contact operation by means of at least one coil (L) forming a tuned resonant circuit with a tuning capacitor (C.sub.A), including a charge pump (10) with two clock inputs (E.sub.1 E.sub.2), wherein the clock inputs (E.sub.1 E.sub.2) of the charge pump (10) are constantly connected to the terminals of the coil (L), at least during the periods of non-contact operation of the integrated circuit, whereby the charge pump, seen from the clock inputs thereof, is a constant component of the tuning capacitor of the tuned resonant circuit.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: November 9, 1999
    Assignee: Inside Technologies
    Inventors: Michel Martin, Jacek Kowalski
  • Patent number: 5981224
    Abstract: A novel expression system using the heat-inducible bovine hsp70A promoter and associated cis-acting elements is disclosed. The system provides for the continuous production of a highly pure, authentic protein, substantially free of infectious viral and cellular protein contaminants.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: November 9, 1999
    Assignee: Biostar Inc.
    Inventors: Jacek Kowalski, Scott Gilbert, Timothy J. Zamb
  • Patent number: 5825882
    Abstract: Encryption circuits and methods, in particular for smart cards, are disclosed. Smart cards without microprocessors may be authenticated very simply by using encryption with a secret card data table on which recursive cycles are executed. During each cycle, a word is read out of the table, said word being at an address that is at least partially defined by the word read out in the previous cycle. The new address preferably consists of several bits from the previous word and a bit from internal card data, external data supplied by a card reader, or a register containing a partial encryption result.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: October 20, 1998
    Assignee: Gemplus Card International
    Inventors: Jacek Kowalski, Michel Martin, Jacques Stern, Antoine Joux
  • Patent number: 5740403
    Abstract: A process to protect against tampering with integrated circuits. During manufacture, a secret code is written in a secret address (102) of a memory (101) of the integrated circuit and an internal logic (103-108) blocks writing into this portion of memory, the testing of the integrated circuit and the read-out of data. In order to unlock the integrated circuit, the secret address is read while applying a secret code to an input of the integrated circuit. A comparison (207) of the secret code as read and the secret code applied to the integrated circuit then either locks or unlocks the integrated circuit. This unlocking is done in irreversible manner. Thus, it is possible to transport integrated circuits between a manufacturer and a remote users, without fear of the circuits being stolen, because if stolen, they would be inoperable without the secret codes.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: April 14, 1998
    Assignee: Gemplus Card International
    Inventor: Jacek Kowalski
  • Patent number: 5733745
    Abstract: A novel expression system using the heat-inducible bovine hsp70A promoter and associated cis-acting elements is disclosed. The system provides for the continuous production of a highly pure, authentic protein, substantially free of infectious viral and cellular protein contaminants.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: March 31, 1998
    Assignee: Biostar Inc.
    Inventors: Jacek Kowalski, Scott Gilbert, Timothy J. Zamb
  • Patent number: 5721440
    Abstract: In a memory cell of an EEPROM or flash-EEPROM memory, the source and the drain of a floating-gate transistor forming the non-volatile memorizing device are connected together. It is shown that the capacitive behavior of the cell is then differentiated at the time of the reading depending on whether it is in a programmed state or in an erased state. This difference in behavior is used to differentiate the logic states.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: February 24, 1998
    Assignee: Gemplus Card International
    Inventor: Jacek Kowalski
  • Patent number: 5576989
    Abstract: In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into N rows of P cells, the weight of the cells of one row in the account being P times the weight of the next-ranking row. The countdown procedure is recurrent and consists in making a search, in scanning the memory according to the rising order of weights, of an erased cell, programming this cell and an erased cell and then erasing the entire row having an immediately lower rank unless the erased cell is located in the first row, and in recommencing this recurrent procedure until an erased cell is found in the first line. The auxiliary cell enables the detection of an abnormal interruption of the recurrent procedure and the restoring of the exact account of the memory which could have been distorted by this abnormal interruption.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: November 19, 1996
    Assignee: Gemplus Card International
    Inventor: Jacek Kowalski
  • Patent number: 5552621
    Abstract: In a memory cell of an EEPROM or flash-EEPROM memory, the source and the drain of a floating-gate transistor forming the non-volatile memorizing device are connected together. It is shown that the capacitive behavior of the cell is then differentiated at the time of the reading depending on whether it is in a programmed state or in an erased state. This difference in behavior is used to differentiate the logic states.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: September 3, 1996
    Assignee: Gemplus Card International
    Inventor: Jacek Kowalski
  • Patent number: 5550919
    Abstract: To resolve the problems related to the divulgation of the algorithms for the transcoding of the secret codes in chip cards, notably prepayment type chip cards, it is planned to limit the number of authentication operations possible by the number of units contained in the card. It is shown that in this case this number, which is generally small, for example about a hundred units, limits the number of attempts that can be made by a fraudulent person trying to penetrate the mysteries of the secret enciphering algorithm.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: August 27, 1996
    Assignee: Gemplus Card International
    Inventor: Jacek Kowalski
  • Patent number: 5534686
    Abstract: The invention relates to chip cards. There is disclosed a chip card (12) with only two contacts intented both to information exchanges (instructions and data) between the card (12) and a card reader and to the power supply of the card (12). According to the invention, the contacts are preferably a clock contact (CLK) used to the synchronization of data and instructions, and a data input/output contact (I/O) used to the transmission of data and instructions from the reader to the card (12) and to the transmission of data from the card (12) to the reader. For the power supply, a full-wave rectifier (bridge of diodes) may be arranged between the two contacts (CLK;I/O). The invention also relates to the communication protocole which allows to use only two contacts (CLK;I/O) while having instructions similar to those of conventional chip cards (initialization of the card, address incrementation of memory cell, reading of the cell, writing, comparison of a confidential code).
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: July 9, 1996
    Assignee: Gemplus Card International
    Inventors: Jacek Kowalski, Jean Sureaud
  • Patent number: 5521084
    Abstract: A novel expression system using the heat-inducible bovine hsp70A promoter and associated cis-acting elements is disclosed. The system provides for the continuous production of a highly pure, authentic protein, substantially free of infectious viral and cellular protein contaminants.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: May 28, 1996
    Assignee: Biostar, Inc.
    Inventors: Jacek Kowalski, Scott Gilbert, Timothy J. Zamb
  • Patent number: 5512852
    Abstract: An automatic trigger circuit including: a two-arm current mirror including a first arm connected between a DC electrical supply and a ground, the first arm including a first transistor including a first source connected to the DC electrical supply, a first gate, and a first drain connected to the first gate; a second transistor including a second gate connected to the DC electrical supply, a second drain connected to the first drain and a second source; a third transistor including a third drain connected to the second source, a third gate for receiving a first level reference voltage, and a third source; and a fourth transistor including a fourth drain connected to the third source and a fourth source connected to the ground; and a second arm connected between the DC electrical supply and the ground, the second arm including a fifth transistor including a fifth source connected to the DC electrical supply, a fifth gate connected to the first gate and a fifth drain; and a sixth transistor including a sixth dr
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: April 30, 1996
    Assignee: Gemplus Card International
    Inventor: Jacek A. Kowalski
  • Patent number: 5473564
    Abstract: In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into N rows of P cells, the weight of the cells of one row in the account being P times the weight of the next-ranking row. The countdown procedure is recurrent and consists in making a search, in scanning the memory according to the rising order of weights, of an erased cell, programming this cell and an erased cell and then erasing the entire row having an immediately lower rank unless the erased cell is located in the first row, and in recommencing this recurrent procedure until an erased cell is found in the first line. The auxiliary cell enables the detection of an abnormal interruption of the recurrent procedure and the restoring of the exact account of the memory which could have been distorted by this abnormal interruption.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: December 5, 1995
    Assignee: Gemplus Card International
    Inventor: Jacek A. Kowalski