Abstract: An integrated circuit, supplied with a supply voltage Vcc, the intergrated circuit including: an antifuse including terminals; and a programming circuit for programming the antifuse, the programming circuit using a programming voltage Vpp that is substantially higher than the supply voltage Vcc, wherein the programming circuit including structure to apply the supply voltage Vcc to the terminals of the antifuse immediately after an application of the programming voltage Vpp to the terminals of the antifuse so that programming of the antifuse is not interrupted.

Abstract: A circuit to produce a voltage Vpp from a lower voltage supply Vcc is useful, for example, to produce the voltage for programming the cells of an electrically programmable memory. The circuit has a load pump (PMP), a regulator (REG) to interrupt the working of the load pump when the voltage Vpp exceeds a predetermined voltage (Vpp0), a transistor (T1) to interrupt the current consumption of the regulator when the load pump is interrupted, and a control circuit (CTRL) to then monitor the voltage Vpp and ascertain that it does not drop by more than a small value dV below Vpp0 and to restart both the load pump and the current supply of the regulator if the voltage drops more than dV.

Abstract: A fuse circuit including: a physical fuse; a detection circuit for the detection of the state of the physical fuse; and an electrically programmable non-volatile memory cell associated with the physical fuse, programmed when the physical fuse is blown and connected to the detection circuit so that, when the electrically programmable non-volatile memory cell is programmed, the electrically programmable non-volatile memory cell confirms the blown state of the physical fuse even if the characteristics of the blown state of the physical fuse change with time.

Abstract: The invention relates to PC-cards.In order to permit communications between readers operating according to several different communication protocols, according to the invention said card comprises:several conversion circuits (CNV1, CNV2, CNV3), each of which is able to convert into instructions performable by the card the electrical signals received from the reader according to a given protocol, each of the different conversion circuits corresponding to a different communication protocol,and a protocol selection circuit (CNVA, L0, L1, L2, L3, G1 to G6), incorporating an auxiliary conversion circuit (CNVA), the latter being able to produce specific instructions performable by the card, said specific instructions being used for the selection of one of the conversion circuits and being produced from electrical signals which can be produced in all the protocols.

Abstract: The MOS cell with adjustable threshold voltage is a cell of the type with a memory that is electrically-erasable and programmable by storage of charges by tunnel effect in a floating gate. To obtain a circuit with adjustable threshold voltage, the cell is first of all "programmed" at zero so that all the charges that may be stored are removed and then it is "erased", with its source grounded, its drain taken to the high potential and its control gate taken to the potential desired for the threshold voltage V.sub.T of the circuit. At the end of this phase, the threshold voltage is adjusted. This device can be applied notably to circuits requiring precise voltage references in MOS technology, namely circuits of the detector or analog-digital converter type.

Abstract: The disclosure relates to counters that require the counting to be done under conditions of high security. In such a counter, starting from a number represented by a certain number of bits, the stages of the counter are successively forced, one after the other, to represent the final number in an order such that at no instant do the contents of the counter represent a number smaller than the initial number. A particular structure is used to count very big numbers while, when the technology is of the EEPROM type. This prevents the stage that changes its state most frequently from being subjected to action more than is physically permitted by the technology used. The disclosed method makes it possible, in chip cards, to prevent the diminishing of memorized values representing substantial values which are, for example, monetary values.

Abstract: The invention concerns interface circuits for chip card readers. It consists of providing link connections between this circuit and the reader, these connections being identical to those established between the circuit and the chip card. An internal switch (102) in the circuit is used to link these connections together, or to a control register (101), which is internal to the circuit, and actuated by an additional control connection. With the invention, it is possible to limit the number of connections between the circuit and the reader and to control the circuit with a software interface which is identical to the control interface of a chip card.

Abstract: A MOS fuse with oxide breakdown based on a MOS cell electrically programmable by tunnel effect and storage of charges at a gate. This cell is converted into a fuse by providing for the application, when the fuse has to break down, of an intense field, greater than the oxide breakdown threshold, in the tunnel window. Thus, the breakdown is irreversible. The disclosed device can be applied notably to fuses designed for the integrated circuits of memory cards.

Abstract: Phenomena of unwanted programming, caused by the substrate currents of an integrated circuit, are prevented by providing for a measurement of these currents and for a circuit invalidating the operation of the integrated circuit when the result of this measurement goes beyond a certain threshold. In a preferred way, the measurement of the substrate current is obtained by making a bipolar type transistor, the base region of which is formed precisely by this substrate, or by making a a field-effect type of transistor, the gate of which and one of the active regions of which are connected to the ground terminal of the circuit. But theses two connections are different. One of the connections is direct while the other is a connection subjected to the fluctuations in the potential of the substrate.

Abstract: A circuit for detecting the high voltage level of a voltage V.sub.cc in MOS technology comprises a voltage source made of at least one P-type MOS transistor and one N-type MOS transistor, and delivers an output voltage VA such that: O<VA<VTN if V.sub.cc .ltoreq.C and VA=Vcc-C+VTN if V.sub.cc >C, VTN being the threshold voltage of the N-type transistor and C being a substantially constant voltage. The circuit further comprises means for delivering an output logic level which switches over when the high voltage level of the voltage V.sub.cc exceeds a predetermined threshold, said means being connected to the voltage source. The invention can be applied to EPROMs or EEPROMs.

Abstract: Between a bit line decoder and the memory of an integrated circuit, there is interposed a gate circuit which is cascade-connected with a logic block of the integrated circuit. This arrangement makes possible the structural testing of the integrated circuit. Structural testing means to read and check the response given on the outputs of the logic blocks for a given state imposed on its inputs. This arrangement results in a reduction of the space required on the integrated circuit for testing, when compared with other solutions, which require specific connection circuits. This arrangement is particularly adapted to integrated circuits with a memory and with decoders that provide access to the memory. The arrangement will find particular application in the testing of memory cards where EPROM or EEPROM circuits are used.

Abstract: The microcircuit card is such that at least one strain-indicating sensor is placed on the microcircuit, in a known state of strain, and is maintained in this state by a protection layer deposited on the microcircuit for as long as this layer is not affected. The microcircuit has means for measuring an electrical value that is characteristic of the strain, and a logic circuit connected to the measuring means to detect the changes in the condition of strain indicating an intrusion into the card.

Abstract: The use of charge pumps to supply bit lines, when programming memory cells connected to a bit line, is avoided by pre-charging this bit line simultaneously with the neutralization of the selection of this bit line. Subsequently, the pre-charging potential is uncoupled and the effects of the neutralization are stopped. It is known that this method of action prevents the breakdown of a single programming potential generator, used to supply all the bit lines. This results in a gain in space in the lay-out of the control circuits of the memory cells in the memory plane. This method can be implemented especially in page mode programming for memories where the memory cells have EEPROM-type floating-gate transistors.

Abstract: The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray thyristor is triggered by artificially making the potential drop in an intermediate region of the pad. The thyristor always comes on suddenly, the current that flows through the thyristor is very high and the phenomenon stops spontaneously when the fuse is melted.

Abstract: To prevent fraudulent action by ill-intentioned users, the detection of the secret codes, contained in a memory card with MOS integrated circuit and transmitted to an input/output unit, is prevented. This is done by interposing a read amplifier in the transmission chain, in the integrated circuit itself. This read amplifier essentially has two parallel-connected identical circuits, designed to take complementary logic states when they receive one and the same logic level to be detected. The result of this is that the electrical comsumption of the amplifier is the same regardless of the logic level transmitted. Thus, it becomes impossible to deduce the nature of the logic level transmitted. As an improvement, the outputs of the detector are provided with bistable circuits which are coupled to each other so as to be capable of taking transitory or spurious information detected into account.

Abstract: A read circuit is disclosed for logic circuit type integrated circuits comprising a memory consisting of a matrix of memory cells. The memory cells are each addressable by rows and columns selected by row and column decoders. The read circuit, which is connected to the memory cells by a line called a bit line, comprises a pre-loading circuit for the bit line and a detection circuit that detects the discharging or non-discharging of the bit line depending on whether the memory cell selected is in the state "0" or "1", and also comprises a means to memorize the state that is read. The circuit further comprises means which make it possible, in read mode, to discharge the bit line regardless of whether the memory cell is in the state "1" or "0" and means that delay the moment of discharge. The invention can be applied to EPROMs or similar memories.

Abstract: To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

Abstract: A read circuit is disclosed for integrated circuits of the logic circuit type, comprising a memory consisting of a matrix of memory cells, the reading of which is done by the detection of a current variation or voltage variation, the memory cells being each addressable by rows and columns selected by row and column decoders, the read circuit being connected to memory cells by a line known as a bit line, and comprising a bit line pre-loading circuit and a detection circuit that detects the conduction or non-conduction of the addressed memory cell. The read circuit comprises a parallel-connected second identical detection circuit, the two detection circuits being connected to a common node of the bit line by means which provide for the simultaneous detection, at each read operation, of a "1" or a "0" regardless of the state of the memory cell addressed, and which provide for obtaining the data read at the output of at least one detection circuit. The invention can be applied to EPROMs in particular.

Abstract: The depassivation of an integrated circuit is detected by using the fact that the passivation coat which covers this circuit participates in the coupling capacitances that exist between parallel metallized lines made on its surface. The variation in one of these capacitances, resulting from depassivation, leads to a modification of the dielectrical induction of a voltage step, emitted on one line, in another line. The resulting variation in the induced voltage is used to produce a logic signal that reveals this depassivation. This logic signal can be used to neutralize the functioning of the integrating circuit to be protected.

Abstract: Disclosed is an integrated circuit comprising an electrically erasable programmable memory, the cells of which comprise a transistor with floating gate which is series connected with an access transistor, wherein, in order to prevent deterioration in the information stored in the transistors with floating gates, due to an excessive read voltage being applied to the cell, the circuit has, firstly, an additional cell constituted like the other cells and programmed in a state where its transistor with floating gate cannot be made conductive, the gate and the source of the transistor with floating gate of the additional cell being grounded, the drain and the gate of the access transistor receiving the memory reading voltage, and, secondly, a threshold comparator connected to the drain of the floating gate transistor to compare the voltage on this drain with the reading voltage and to give a signal in the event of any abnormal drop in the voltage at the drain.