Patents by Inventor Jacek Rudzki

Jacek Rudzki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170216920
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Application
    Filed: September 9, 2015
    Publication date: August 3, 2017
    Applicant: Danfoss Silicon Power GMBH
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Patent number: 9613929
    Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal molded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the molded body used according to the method for contacting are selected corresponding to the magnitude.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: April 4, 2017
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki
  • Publication number: 20160225738
    Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal moulded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the moulded body used according to the method for contacting are selected corresponding to the magnitude.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki
  • Patent number: 9318421
    Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal molded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the molded body used according to the method for contacting are selected corresponding to the magnitude.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 19, 2016
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki
  • Publication number: 20140230989
    Abstract: The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal moulded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal moulded bodies, and applying the metal moulded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the moulded body.
    Type: Application
    Filed: September 10, 2012
    Publication date: August 21, 2014
    Applicant: DANFOSS SILICON POWER GMBH
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki
  • Publication number: 20140225247
    Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal moulded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the moulded body used according to the method for contacting are selected corresponding to the magnitude.
    Type: Application
    Filed: September 10, 2012
    Publication date: August 14, 2014
    Applicant: DANFOSS SILICON POWER GMBH
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki