Patents by Inventor Jack Chen

Jack Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8368508
    Abstract: To key an identification code of a controlling member to a code reader of a function controller for controlling a function, each controlling member is fitted with a card reader and is configured to adopt the code on the card as the identification code to be attached as the identification portion of any message imparted into a signal line. In similar fashion, each of the function controllers includes a card reader for reading a card bearing a code and the function controller is configured to adopt the code read from the card as being the identification code sought by the function controller as identifying a message as originating from its associated controlling member.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: February 5, 2013
    Inventor: Jack Chen
  • Patent number: 8316358
    Abstract: A method and apparatus are set forth for creating a Document Object Model of an XML document of predetermined type, comprising a first process for receiving and opening a compressed input file containing the XML document; a second process for opening and parsing the contents of a relationships file to create a map of name-value pairs and detecting a value for identifying the predetermined type from among a plurality of types of XML documents; and a further process for parsing data in the XML document according to the predetermined type, and building the Document Object Model.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: November 20, 2012
    Assignee: Research In Motion Limited
    Inventors: Jack Chen, David Weintraub, Jian Frank Li
  • Patent number: 8263876
    Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 11, 2012
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Sung-Yi Hsiao, Jack Chen
  • Patent number: 8185242
    Abstract: Methods and systems to optimize wafer placement repeatability in semiconductor manufacturing equipment using a controlled series of wafer movements are provided. In one embodiment, a preliminary station calibration is performed to teach a robot position for each station interfaced to facets of a vacuum transfer module used in semiconductor manufacturing. The method also calibrates the system to obtain compensation parameters that take into account the station where the wafer is to be placed, position of sensors in each facet, and offsets derived from performing extend and retract operations of a robot arm. In another embodiment where the robot includes two arms, the method calibrates the system to compensate for differences derived from using one arm or the other. During manufacturing, the wafers are placed in the different stations using the compensation parameters.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: May 22, 2012
    Assignee: Lam Research Corporation
    Inventors: Scott Wong, Jeffrey Lin, Andrew D. Bailey, III, Jack Chen, Benjamin W. Mooring, Chung Ho Huang
  • Publication number: 20120122254
    Abstract: A white light-emitting diode package structure for simplifying package process includes a substrate unit, a light-emitting unit, a phosphor unit and a conductive unit. The light-emitting unit is disposed on the substrate, and the light-emitting unit has a positive conductive layer and a negative conductive layer. The phosphor unit has a phosphor layer formed on the light-emitting unit and at least two openings for respectively exposing one partial surface of the positive electrode layer and one partial surface of the negative electrode layer. The conductive unit has at least two conductive wires respectively passing through the two openings in order to electrically connect the positive electrode layer with the substrate unit and electrically connect the negative electrode layer with the substrate unit.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 17, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Publication number: 20120119231
    Abstract: An LED package structure with a deposited-type phosphor layer includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes at least one circuit substrate. The light-emitting unit includes a plurality of LED chips disposed on and electrically connected to the at least one circuit substrate. The package unit includes at least one package resin body formed by a mold structure. The at least one package resin body is formed on the at least one circuit substrate to cover the LED chips, and the at least one package resin body includes a continuous phosphor layer formed therein and deposited on outer surfaces of the LED chips by centrifugal force. Hence, the instant disclosure provides the continuous phosphor layer with the deposited phosphor powders for covering the outer surfaces of the LED chips, thus the light-emitting efficiency of the LED package structure can be increased actually.
    Type: Application
    Filed: July 13, 2011
    Publication date: May 17, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, YU-JEN CHENG, JACK CHEN
  • Publication number: 20120106171
    Abstract: An LED package structure includes a conductive substrate unit, a first insulative unit, a second insulative unit, a light-emitting unit and a package unit. The conductive substrate unit includes at least two conductive bases and at least one gap is formed between the two conductive bases. The first insulative unit includes at least one first insulative layer filled in the gap to join the two conductive bases. The second insulative unit includes at least one second insulative layer disposed on the conductive substrate unit and a plurality of openings passing through the second insulative layer for exposing one part of the top surface of each conductive base. The light-emitting unit includes at least one light-emitting element passing one of the openings and electrically connected between the two conductive bases. The package unit includes a package resin body disposed on the second insulative unit to cover the light-emitting element.
    Type: Application
    Filed: July 6, 2011
    Publication date: May 3, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, YU-JEN CHENG, JACK CHEN
  • Publication number: 20120096710
    Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 26, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Patent number: 8135485
    Abstract: A method for aligning a substrate to a process center of a support mechanism is provided. The method includes determining substrate thickness after substrate processing at a plurality of orientations and at a plurality of radial distances from a geometric center of the substrate. The method also includes deriving a set of process rate values from substrate thickness and process duration. The method further includes creating for a process rate an off-centered plot, which represents a substantially concentric circle whose points are a circumference of the off-centered plot having substantially the first process rate. The method yet also includes applying a curve-fitting equation to the off-centered plot to determine a set of parameters. The method yet further includes teaching a set of robot arms the set of parameters, thereby enabling the set of robot arms to align another substrate that is supported by the support mechanism with the process center.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: March 13, 2012
    Assignee: Lam Research Corporation
    Inventors: Jack Chen, Andrew D. Bailey, III, Ben Mooring, Stephen J Cain
  • Patent number: 8131875
    Abstract: Systems and methods, including computer software implementations, involve identifying a first set of device capabilities associated with an electronic device. The first set of device capabilities include one or more device capabilities. A description of the first set of device capabilities is provided to a remote source, and a first device profile identifier is received from the remote source. The first device profile identifier is associated with the first set of device capabilities. The first device profile identifier is stored on the electronic device, and the received first device profile identifier is included in a communication to the remote source.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: March 6, 2012
    Assignee: Adobe Systems Incorporated
    Inventors: Jack Chen, Rupen Chanda
  • Publication number: 20120037937
    Abstract: An LED package structure includes a substrate unit, a conductive unit, a heat-dissipating unit, a light-emitting unit and a package unit. The substrate unit includes an insulating substrate. The conductive unit includes two top conductive pads disposed on top surface of the insulating substrate, two bottom conductive pads disposed on bottom surface of the insulating substrate, and a plurality of penetrating conductive posts passing the insulating substrate. The two top conducive pads respectively electrically connect the two bottom conductive pads through the penetrating conductive posts. The heat-dissipating unit includes a top heat-dissipating block and a bottom heat-dissipating block respectively disposed on top and bottom surfaces of the insulating substrate. The light-emitting unit includes a light-emitting element on the top heat-dissipating block and electrically connected between the two top conductive pads.
    Type: Application
    Filed: January 10, 2011
    Publication date: February 16, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Publication number: 20120009699
    Abstract: A wafer level LED package structure for increasing light-emitting efficiency includes: a light-emitting unit, an insulating unit, two first conductive units and two second conductive units. The light-emitting unit has a light-emitting body, a positive conductive layer, a negative conductive layer, and a reflecting insulating layer formed between the positive conductive layer and the negative conductive layer. The light-emitting body has a bottom material layer and a top material layer. The insulating unit is formed around an outer area of a top surface of the bottom material layer and formed on a top surface of the reflecting insulating layer. One first conductive unit is formed on one part of the positive conductive layer and the insulating unit, and another first conductive unit is formed on one part of the negative conductive layer and the insulating unit. The two second conductive units are respectively formed on the two first conductive units.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Publication number: 20110304020
    Abstract: A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: HARVATEK CORPORATION
    Inventors: BILY WANG, SUNG-YI HSIAO, JACK CHEN
  • Publication number: 20110287323
    Abstract: A battery core is made from a strip of insulating material folded longitudinally to form parallel panels. In one embodiment there are four panels and in another five panels. A positive electrode strip has an exposed foil center strip and positive electrode material along both edges. The positive electrode is folded around one fold of the insulator with the strip of foil exposed at the fold. A negative electrode strip has an exposed center strip and negative electrode material along both edges. The negative electrode is folded around a different fold of the insulator with the strip of foil exposed.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 24, 2011
    Inventor: Jack Chen
  • Patent number: 8056419
    Abstract: An artificial sensor comprises at least one substrate, and a plurality of flow sensors disposed on the at least one substrate for providing a plurality of spatial-temporally varying signals representing a hydrodynamic stimulus. The plurality of flow sensors are spatially distributed on the at least one substrate. A processor is coupled to the plurality of flow sensors for receiving the signals and determining spatial-temporal information from the received signals.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: November 15, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Chang Liu, Jonathan Engel, Jack Chen
  • Patent number: 8053885
    Abstract: A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 8, 2011
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Sung-Yi Hsiao, Jack Chen
  • Patent number: 8041372
    Abstract: Systems and methods, including computer software products, can be implemented for selecting data on a mobile device on which multiple channels are defined. Each channel can be adapted to receive a predetermined type of content for access on the mobile device. Multiple languages may also be defined on the device, and multiple data sets for at least one of the channels are received, wherein each data set is configured for presentation in a different one of the languages. One of the data sets may be selected based on a current location.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 18, 2011
    Assignee: Adobe Systems Incorporated
    Inventors: Steve Minns, Rupen Chanda, Jack Chen
  • Patent number: 8036946
    Abstract: A method for making an inference based on cumulative data. The method utilizes video, audio, and biometric devices to observe a retail environment for the presence of a customer. Once a customer is present, the method identifies every cohort to which the customer corresponds. Next, the method observes the customer as they peruse aisles in the retail environment. When the customer selects a product, the method identifies the selected product and searches the cohorts for alternate products to offer the customer. The method offers one alternate product to the customer and records to the cohorts whether the customer thereinafter accepts the method's offer and selects the alternate product or rejects the method's offer and continues perusing the retail environment aisles. The method continues observing the customer and offering alternate product until the customer leaves the retail environment.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert Lee Angell, Vinod A. Bijlani, Jack Chen, Robert R. Friedlander, James R. Kraemer, Le Gang Wu
  • Publication number: 20110232566
    Abstract: A method for etching a bevel edge of a substrate in a processing chamber is provided. The method includes flowing an inert gas into a center region of the processing chamber defined above a center region of the substrate and flowing a mixture of an inert gas and a processing gas over an edge region of the substrate. The method further includes striking a plasma in the edge region, wherein the flow of the inert gas and the flow of the mixture maintain a mass fraction of the processing gas substantially constant. A processing chamber configured to clean a bevel edge of a substrate is also provided.
    Type: Application
    Filed: June 9, 2011
    Publication date: September 29, 2011
    Inventors: Jack Chen, Andrew D. Bailey, III, Iqbal Shareef
  • Patent number: D645421
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: September 20, 2011
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Sung-Yi Hsiao, Jack Chen