Patents by Inventor Jack H. Yuan

Jack H. Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7858472
    Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: December 28, 2010
    Assignee: SanDisk Corporation
    Inventors: Jack H. Yuan, Eliyahou Harari, Yupin K. Fong, George Samachisa
  • Patent number: 7834392
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: November 16, 2010
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Publication number: 20090286370
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Application
    Filed: July 27, 2009
    Publication date: November 19, 2009
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Patent number: 7615820
    Abstract: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. Storage elements for a NAND type flash memory system, for example, can be fabricated by etching the substrate to form the trench after or as part of etching to form NAND string active areas. This can ensure alignment of the NAND string active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas. A subsequently formed inter-gate dielectric layer and control gate layer can fill the open area to provide sidewall coupling between control gates and floating gates.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: November 10, 2009
    Assignee: SanDisk Corporation
    Inventor: Jack H Yuan
  • Patent number: 7579247
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 25, 2009
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Patent number: 7541237
    Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: June 2, 2009
    Assignee: Sandisk Corporation
    Inventors: Jack H. Yuan, Jacob Haskell
  • Patent number: 7517756
    Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: April 14, 2009
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan
  • Patent number: 7491999
    Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 17, 2009
    Assignee: Sandisk Corporation
    Inventors: Eliyahou Harari, Jack H. Yuan, George Samachisa, Henry Chien
  • Patent number: 7479677
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: January 20, 2009
    Assignee: Sandisk Corporation
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Publication number: 20080211007
    Abstract: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. Storage elements for a NAND type flash memory system, for example, can be fabricated by etching the substrate to form the trench after or as part of etching to form NAND string active areas. This can ensure alignment of the NAND string active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas. A subsequently formed inter-gate dielectric layer and control gate layer can fill the open area to provide sidewall coupling between control gates and floating gates.
    Type: Application
    Filed: May 13, 2008
    Publication date: September 4, 2008
    Inventor: Jack H. Yuan
  • Patent number: 7416956
    Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: August 26, 2008
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan
  • Patent number: 7402886
    Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: July 22, 2008
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan
  • Publication number: 20080157169
    Abstract: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventor: Jack H. Yuan
  • Publication number: 20080160680
    Abstract: Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventor: Jack H. Yuan
  • Patent number: 7381615
    Abstract: Methods for self-aligned trench filling to isolate active regions in high-density integrated circuits are provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. A conductive layer used for the charge storage region of memory cells can be formed prior to formation of the trench isolation region. The trench can be etched after or as part of etching to form the individual charge storage regions. This can ensure alignment of active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: June 3, 2008
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan
  • Patent number: 7341918
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 11, 2008
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Patent number: 7342279
    Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 11, 2008
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
  • Patent number: 7288455
    Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: October 30, 2007
    Assignee: SanDisk Corporation
    Inventors: Jack H. Yuan, Jacob Haskell
  • Patent number: 7211866
    Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: May 1, 2007
    Assignee: Sandisk Corporation
    Inventors: Jack H. Yuan, Eliyahou Harari, Yupin K. Fong, George Samachisa
  • Patent number: 7170131
    Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: January 30, 2007
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan