Abstract: Methods and systems are disclosed related to determining whether there is a proper fit between a user interface and a face of a user. The methods and systems involve generating seal information associated with a seal region between a face of a user and a current user interface donned on the face of the user. The methods and systems are further related to analyzing the seal information to determine whether a leak exists in the seal region. If the leak exists, the systems and methods include analyzing the seal information to determine a location of the leak within the seal region. The systems and methods further include determining a new user interface to replace the current user interface based on the current user interface and the location of the leak.

Abstract: The present invention relates to compositions and methods for preventing and reducing inflammation and preventing and treating diseases and disorders associated with inflammation. It has been shown that CRADD plays a pivotal role in maintaining the integrity of endothelial monolayers. The recombinant cell-penetrating CRADD protein (CP-CRADD)-based compositions and methods described herein provide for the development of a novel treatment for inflammatory vascular disorders including cardiovascular, cerebrovascular, respiratory, gastrointestinal, and renal systems.

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

Abstract: Methods and apparatuses for video processing. In one aspect, filtering is applied after applying a set of offset values to one or more coefficients. The application of an offset value may be based on a determination as to whether the coefficient meets a threshold value.

Abstract: The present invention provides engineered glycosyltransferase (GT) enzymes, polypeptides having GT activity, and polynucleotides encoding these enzymes, as well as vectors and host cells comprising these polynucleotides and polypeptides. The present invention provides engineered sucrose synthase (SuS) enzymes, polypeptides having SuS activity, and polynucleotides encoding these enzymes, as well as vectors and host cells comprising these polynucleotides and polypeptides. The present invention also provides compositions comprising the GT enzymes and methods of using the engineered GT enzymes to make products with ?-glucose linkages. The present invention further provides compositions and methods for the production of rebaudiosides (e.g., rebaudioside M, rebaudioside A, rebaudioside I, and rebaudioside D). The present invention also provides compositions comprising the SuS enzymes and methods of using them. Methods for producing GT and SuS enzymes are also provided.

Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.

Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.

Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.

Abstract: A hardware accelerator can receive, from a host processor, a slice of input data at a time-step. The hardware accelerator can process the input data using a machine learning model deployed on the hardware accelerator to compute a respective probability among multiple probabilities for each of multiple classes. The respective probability for each class being a likelihood that content in the slice belongs to the class. The hardware accelerator can determine, from the multiple probabilities, a preset number of highest probabilities for the slice of input data. The hardware accelerator can transmit the preset number of highest probabilities for the slice to the host processor. Related apparatus, systems, techniques and articles are also described.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training giant neural networks. One of the methods includes obtaining data indicating a neural network comprising a plurality of layers; for each layer in a subset of the plurality of layers: assigning a subset of the plurality of computing units to at least partially perform inference computations associated with the layer; determining a memory size and a common memory address for the respective addressable memory unit of each computing unit assigned for the layer; and generating a shared instruction comprising a memory allocation instruction that, when executed by each of the subset of the plurality of computing units, causes the computing unit to store a result of performing inference computations associated with the layer in the determined common memory address with the determined memory size in the addressable memory of the computing unit.

Abstract: Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.

Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.

Abstract: A lock device for locking the sliding door comprises a first lock portion and a transmission portion. The transmission portion may move along relative to the first lock portion a predetermined path, so that the transmission portion may bring the sliding door to move along the predetermined path to open or close the sliding door. The transmission portion has a plurality of successively arranged mating portions for locking with the first lock portion. The first lock portion has a first position in which the first lock portion is locked with the transmission portion and a second position in which the first lock portion is released from the transmission portion. The transmission portion may be locked in different positions along the predetermined path by matching the first lock portion 110 with different mating portions, so that the sliding door can be locked in different positions.

Abstract: An input device is shared between a first remote desktop having a first display image, which is displayed on a first display of a first client device, and a second remote desktop having a second display image, which is displayed on a second display of a second client device. Upon detecting that an input pointer of the input device currently displayed within the first display image on the first display, is moved across an edge of the first remote desktop that corresponds to a virtual boundary between the first remote desktop and the second remote desktop, instructions are issued to a first remote computing device that is hosting the first remote desktop to discontinue receiving inputs made with the input device and a second remote computing device that is hosting the second remote desktop to begin receiving inputs made with the input device.