Patents by Inventor Jack O. Chu
Jack O. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8861728Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.Type: GrantFiled: October 17, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Gregory M. Fritz, Harold J. Hovel, Young-Hee Kim, Dirk Pfeiffer, Kenneth P. Rodbell
-
Publication number: 20140252501Abstract: At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening.Type: ApplicationFiled: September 12, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Szu-Lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-Bang Yau
-
Patent number: 8828762Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.Type: GrantFiled: October 18, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. DiMitrakopoulos, Alfred Grill, Timothy J. McArdle, Dirk Pfeiffer, Katherine L. Saenger, Robert L. Wisnieff
-
Publication number: 20140217468Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Jack O. Chu, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
-
Publication number: 20140220766Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.Type: ApplicationFiled: August 14, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei CHENG, JACK O. CHU, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
-
Publication number: 20140217356Abstract: An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CAN BAYRAM, JACK O. CHU, CHRISTOS DIMITRAKOPOULOS, JEEHWAN KIM, HONGSIK PARK, DEVENDRA K. SADANA
-
Publication number: 20140103286Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.Type: ApplicationFiled: October 17, 2012Publication date: April 17, 2014Applicant: International Business Machines CorporationInventors: Jack O. Chu, Gregory M. Fritz, Harold J. Hovel, Young-Hee Kim, Dirk Pfeiffer, Kenneth P. Rodbell
-
Publication number: 20130285014Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
-
Patent number: 8569803Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: August 13, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
-
Patent number: 8541769Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: GrantFiled: November 9, 2010Date of Patent: September 24, 2013Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
-
Patent number: 8441042Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: GrantFiled: September 17, 2009Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
-
Patent number: 8405127Abstract: In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base.Type: GrantFiled: February 20, 2008Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Jack O. Chu, Francois Pagette
-
Publication number: 20130048061Abstract: A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CHENG-WEI CHENG, Jack O. Chu, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
-
Publication number: 20120319078Abstract: A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.Type: ApplicationFiled: August 28, 2012Publication date: December 20, 2012Applicant: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Chun-Yung Sung, Robert L. Wisnieff
-
Publication number: 20120305929Abstract: This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff, Kerry Bernstein, Stephen W. Bedell
-
Publication number: 20120193603Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Alfred Grill, Chun-yung Sung
-
Publication number: 20120190155Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Jack O. Chu, Guy M. Cohen, John A. Ott, Michael J. Rooks, Paul M. Solomon
-
Patent number: 8187955Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.Type: GrantFiled: August 24, 2009Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Alfred Grill, Chun-yung Sung
-
Patent number: 8178382Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: GrantFiled: January 13, 2011Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurri A. Vlasov, Ying Zhang
-
Publication number: 20120112164Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: ApplicationFiled: November 9, 2010Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff