Patents by Inventor Jack Oon Chu

Jack Oon Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10128343
    Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Publication number: 20180197961
    Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Patent number: 9947755
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer including silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer including transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer including transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Patent number: 9853109
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Publication number: 20170092727
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Publication number: 20170092722
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: April 22, 2016
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Patent number: 9385122
    Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Szu-Lin Cheng, Jack Oon Chu, Isaac Lauer, Jeng-Bang Yau
  • Publication number: 20150221643
    Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Inventors: Szu-Lin Cheng, Jack Oon Chu, Isaac Lauer, Jeng-Bang Yau
  • Patent number: 9059205
    Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Szu-Lin Cheng, Jack Oon Chu, Isaac Lauer, Jeng-Bang Yau
  • Publication number: 20150048428
    Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Szu-Lin Cheng, Jack Oon Chu, Isaac Lauer, Jeng-Bang Yau
  • Patent number: 7906413
    Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Frank Cardone, Jack Oon Chu, Khalid EzzEldin Ismail
  • Patent number: 7902012
    Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Qiqing Christine Ouyang, Jack Oon Chu
  • Patent number: 7790538
    Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
    Type: Grant
    Filed: May 10, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
  • Patent number: 7790566
    Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Deborah Ann Neumayer
  • Publication number: 20100159658
    Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
    Type: Application
    Filed: August 3, 2009
    Publication date: June 24, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qiqing Christine Ouyang, Jack Oon Chu
  • Patent number: 7713829
    Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Douglas Duane Coolbaugh, James Stuart Dunn, David R. Greenberg, David L. Harame, Basanth Jagannathan, Robb Allen Johnson, Louis D. Lanzerotti, Kathryn Turner Schonenberg, Ryan Wayne Wuthrich
  • Patent number: 7679121
    Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Qiqing Christine Ouyang, Jack Oon Chu
  • Patent number: 7678638
    Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Bruce B. Doris, Meikei Ieong, Jing Wang
  • Publication number: 20090267052
    Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
    Type: Application
    Filed: July 29, 2008
    Publication date: October 29, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Oon Chu, David R. DiMilia, Lijuan Huang
  • Patent number: 7608496
    Abstract: A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventor: Jack Oon Chu